BlockRAM: Write before read so that reads the next cycle return the right answer.
[firearm.git] / BlockRAM.v
index 30f7515..e0eceeb 100644 (file)
@@ -12,7 +12,7 @@ module BlockRAM(
         * 0x00004000.  rdata and ready must be driven to zero if the
         * address is not within the range of this module.
         */
-       wire decode = (bus_addr & ~32'h00003FFF) == 32'h00000000;
+       wire decode = bus_addr[31:14] == 18'b0;
        wire [13:0] ramaddr = {bus_addr[13:2], 2'b0};   /* mask off lower two bits
                                                         * for word alignment */
 
@@ -31,7 +31,7 @@ module BlockRAM(
        always @(posedge clk)
        begin
                if (bus_wr && decode)
-                       data[ramaddr[13:2]] <= bus_wdata;
+                       data[ramaddr[13:2]] = bus_wdata;
                
                /* This is not allowed to be conditional -- stupid Xilinx
                 * blockram. */
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