BlockRAM: Write before read so that reads the next cycle return the right answer.

[firearm.git] / Execute.v

diff --git a/Execute.v b/Execute.v
index ab204a0610a41065c5390366a38ab610b52b42e3..65825810a42b8b468504f9af2b072d9bbc635aae 100644 (file)
--- a/Execute.v
+++ b/Execute.v
@@ -57,7 +57,7 @@ module Execute(
                .in0(alu_in0), .in1(alu_in1), .cpsr(cpsr), .op(alu_op),
                .setflags(alu_setflags), .shifter_carry(carry),
                .result(alu_result), .cpsr_out(alu_outcpsr), .setres(alu_setres));
-       
+
        always @(posedge clk)
        begin
                if (!stall)
@@ -75,6 +75,13 @@ module Execute(
                        outop2 <= op2;
                end
        end
+       
+       reg delayedflush = 0;
+       always @(posedge clk)
+               if (flush && outstall /* halp! I can't do it now, maybe later? */)
+                       delayedflush <= 1;
+               else if (!outstall /* anything has been handled this time around */)
+                       delayedflush <= 0;
 
        reg prevstall = 0;
        always @(posedge clk)
@@ -83,7 +90,7 @@ module Execute(
        always @(*)
        begin
                outstall = stall;
-               next_outbubble = inbubble | flush;
+               next_outbubble = inbubble | flush | delayedflush;
                next_outcpsr = cpsr;
                next_outspsr = spsr;
                next_write_reg = 0;
@@ -114,8 +121,8 @@ module Execute(
                                mult_in1 = op2 /* Rs */;
                                $display("New MUL instruction");
                        end
-                       outstall = stall | ((!prevstall | !mult_done) && !inbubble);
-                       next_outbubble = inbubble | !mult_done | !prevstall;
+                       outstall = outstall | ((!prevstall | !mult_done) && !inbubble);
+                       next_outbubble = next_outbubble | !mult_done | !prevstall;
                        next_outcpsr = insn[20] /* S */ ? {mult_result[31] /* N */, mult_result == 0 /* Z */, 1'b0 /* C */, cpsr[28] /* V */, cpsr[27:0]} : cpsr;
                        next_write_reg = 1;
                        next_write_num = insn[19:16] /* Rd -- why the fuck isn't this the same place as ALU */;
@@ -171,7 +178,7 @@ module Execute(
                begin end
                `DECODE_BRANCH:
                begin
-                       if(!inbubble && !flush) begin
+                       if(!inbubble && !flush && !delayedflush) begin
                                jmppc = pc + op0 + 32'h8;
                                if(insn[24]) begin
                                        next_write_reg = 1;
@@ -251,7 +258,7 @@ module ALU(
 
        assign sum = {1'b0, in0} + {1'b0, in1};
        assign diff = {1'b0, in0} - {1'b0, in1};
-       assign rdiff = {1'b0, in1} + {1'b0, in0};
+       assign rdiff = {1'b0, in1} - {1'b0, in0};
        assign sum_v = (in0[31] ^~ in1[31]) & (sum[31] ^ in0[31]);
        assign diff_v = (in0[31] ^ in1[31]) & (diff[31] ^ in0[31]);
        assign rdiff_v = (in0[31] ^ in1[31]) & (rdiff[31] ^ in1[31]);