+ next_write_num = insn_3a[15:12];
+ next_write_data = cp_read;
+ end else begin
+ next_outcpsr = {cp_read[31:28], cpsr_3a[27:0]};
+ next_outcpsrup = 1;
+ end
+ end
+ endcase
+ end
+
+ /* Bus/address control logic. */
+ always @(*)
+ begin
+ dc__rd_req_3a = 1'b0;
+ dc__wr_req_3a = 1'b0;
+ offset = prev_offset;
+ addr = prevaddr;
+ raddr = 32'hxxxxxxxx;
+ dc__addr_3a = 32'hxxxxxxxx;
+ dc__data_size_3a = 3'bxxx;
+
+ casez(insn_3a)
+ `DECODE_ALU_SWP: if(!bubble_3a) begin
+ dc__addr_3a = {op0_3a[31:2], 2'b0};
+ dc__data_size_3a = insn_3a[22] ? 3'b001 : 3'b100;
+ case(swp_state)
+ `SWP_READING:
+ dc__rd_req_3a = 1'b1;
+ `SWP_WRITING:
+ dc__wr_req_3a = 1'b1;
+ default: begin end
+ endcase
+ end
+ `DECODE_ALU_MULT: begin
+ dc__rd_req_3a = 1'b0; /* XXX workaround for Xilinx bug */
+ dc__wr_req_3a = 1'b0;
+ offset = prev_offset;
+ addr = prevaddr;
+ end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
+ addr = insn_3a[23] ? op0_3a + op1_3a : op0_3a - op1_3a; /* up/down select */
+ raddr = insn_3a[24] ? op0_3a : addr; /* pre/post increment */
+ dc__addr_3a = raddr;
+ /* rotate to correct position */
+ case(insn_3a[6:5])
+ 2'b01: /* unsigned half */
+ dc__data_size_3a = 3'b010;
+ 2'b10: /* signed byte */
+ dc__data_size_3a = 3'b001;
+ 2'b11: /* signed half */
+ dc__data_size_3a = 3'b010;
+ default: begin
+ dc__data_size_3a = 3'bxxx;
+ end
+ endcase
+
+ case(lsrh_state)
+ `LSRH_MEMIO: begin
+ dc__rd_req_3a = insn_3a[20];
+ dc__wr_req_3a = ~insn_3a[20];
+ end
+ `LSRH_BASEWB: begin end
+ `LSRH_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!bubble_3a) begin
+ addr = insn_3a[23] ? op0_3a + op1_3a : op0_3a - op1_3a; /* up/down select */
+ raddr = insn_3a[24] ? addr : op0_3a; /* pre/post increment */
+ dc__addr_3a = raddr;
+ dc__data_size_3a = insn_3a[22] ? 3'b001 : 3'b100;
+ case (lsr_state)
+ `LSR_MEMIO: begin
+ dc__rd_req_3a = insn_3a[20] /* L */ || insn_3a[22] /* B */;
+ dc__wr_req_3a = !insn_3a[20] /* L */ && !insn_3a[22]/* B */;
+ end
+ `LSR_STRB_WR:
+ dc__wr_req_3a = 1;
+ `LSR_BASEWB: begin end
+ `LSR_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDMSTM: if (!bubble_3a) begin
+ dc__data_size_3a = 3'b100;
+ case (lsm_state)
+ `LSM_SETUP:
+ offset = 6'b0;
+ `LSM_MEMIO: begin
+ dc__rd_req_3a = insn_3a[20];
+ dc__wr_req_3a = ~insn_3a[20];
+ offset = prev_offset + 6'h4;
+ offset_sel = insn_3a[24] ? offset : prev_offset;
+ raddr = insn_3a[23] ? op0_3a + {26'b0, offset_sel} : op0_3a - {26'b0, offset_sel};
+ dc__addr_3a = raddr;
+ end
+ `LSM_BASEWB: begin end
+ `LSM_WBFLUSH: begin end
+ default: begin end
+ endcase
+ end
+ `DECODE_LDCSTC: begin end
+ `DECODE_CDP: begin end
+ `DECODE_MRCMCR: begin end
+ default: begin end
+ endcase
+ end
+
+ /* Bus data control logic. */
+ always @(*)
+ begin
+ dc__wr_data_3a = 32'hxxxxxxxx;
+
+ casez(insn_3a)
+ `DECODE_ALU_SWP: if(!bubble_3a)
+ if (swp_state == `SWP_WRITING)
+ dc__wr_data_3a = insn_3a[22] ? {4{op1_3a[7:0]}} : op1_3a;
+ `DECODE_ALU_MULT: begin end
+ `DECODE_ALU_HDATA_REG,
+ `DECODE_ALU_HDATA_IMM: if(!bubble_3a)
+ case(insn_3a[6:5])
+ 2'b01: /* unsigned half */
+ dc__wr_data_3a = {2{op2_3a[15:0]}}; /* XXX need to store halfword */
+ 2'b10: /* signed byte */
+ dc__wr_data_3a = {4{op2_3a[7:0]}};
+ 2'b11: /* signed half */
+ dc__wr_data_3a = {2{op2_3a[15:0]}};
+ default: begin end
+ endcase
+ `DECODE_LDRSTR_UNDEFINED: begin end
+ `DECODE_LDRSTR: if(!bubble_3a) begin
+ dc__wr_data_3a = insn_3a[22] ? {24'h0, {op2_3a[7:0]}} : op2_3a;
+ if (lsr_state == `LSR_STRB_WR)
+ case (dc__addr_3a[1:0])
+ 2'b00: dc__wr_data_3a = {rd_data_latch[31:8], op2_3a[7:0]};
+ 2'b01: dc__wr_data_3a = {rd_data_latch[31:16], op2_3a[7:0], rd_data_latch[7:0]};
+ 2'b10: dc__wr_data_3a = {rd_data_latch[31:24], op2_3a[7:0], rd_data_latch[15:0]};
+ 2'b11: dc__wr_data_3a = {op2_3a[7:0], rd_data_latch[23:0]};
+ endcase
+ end
+ `DECODE_LDMSTM: if (!bubble_3a)
+ if (lsm_state == `LSM_MEMIO)
+ dc__wr_data_3a = (cur_reg == 4'hF) ? (pc_3a + 12) : rf__rdata_3_3a;
+ `DECODE_LDCSTC: begin end
+ `DECODE_CDP: begin end
+ `DECODE_MRCMCR: begin end
+ default: begin end
+ endcase
+ end
+
+ /* LDM/STM register control logic. */
+ always @(posedge clk)
+ if (!dc__rw_wait_3a || lsm_state != `LSM_MEMIO)
+ begin
+ prev_reg <= cur_reg;
+ regs <= next_regs;
+ end
+
+ always @(*)
+ begin
+ rf__read_3_3a = 4'hx;
+ cur_reg = prev_reg;
+ next_regs = regs;
+
+ casez(insn_3a)
+ `DECODE_LDMSTM: if(!bubble_3a) begin
+ case(lsm_state)
+ `LSM_SETUP:
+ next_regs = insn_3a[23] /* U */ ? op1_3a[15:0] : {op1_3a[0], op1_3a[1], op1_3a[2], op1_3a[3], op1_3a[4], op1_3a[5], op1_3a[6], op1_3a[7],
+ op1_3a[8], op1_3a[9], op1_3a[10], op1_3a[11], op1_3a[12], op1_3a[13], op1_3a[14], op1_3a[15]};
+ `LSM_MEMIO: begin
+ casez(regs)
+ 16'b???????????????1: begin
+ cur_reg = 4'h0;
+ next_regs = {regs[15:1], 1'b0};