Hit all with the integrate.
[firearm.git] / Memory.v
index c9d080d..eb0f69f 100644 (file)
--- a/Memory.v
+++ b/Memory.v
@@ -4,6 +4,8 @@ module Memory(
        input clk,
        input Nrst,
 
+       input flush,
+
        /* bus interface */
        output reg [31:0] busaddr,
        output reg rd_req,
@@ -16,6 +18,14 @@ module Memory(
        output reg [3:0] st_read,
        input [31:0] st_data,
        
+       /* Coprocessor interface */
+       output reg cp_req,
+       input cp_ack,
+       input cp_busy,
+       output cp_rnw,  /* 1 = read from CP, 0 = write to CP */
+       input [31:0] cp_read,
+       output reg [31:0] cp_write,
+       
        /* stage inputs */
        input inbubble,
        input [31:0] pc,
@@ -37,8 +47,8 @@ module Memory(
        output reg out_write_reg = 1'b0,
        output reg [3:0] out_write_num = 4'bxxxx,
        output reg [31:0] out_write_data = 32'hxxxxxxxx,
-       output reg [31:0] out_spsr = 32'hxxxxxxxx,
-       output reg [31:0] out_cpsr = 32'hxxxxxxxx
+       output reg [31:0] outspsr = 32'hxxxxxxxx,
+       output reg [31:0] outcpsr = 32'hxxxxxxxx
        );
 
        reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
@@ -72,8 +82,8 @@ module Memory(
                prev_reg <= cur_reg;
                prev_offset <= offset;
                prev_raddr <= raddr;
-               out_cpsr <= next_outcpsr;
-               out_spsr <= spsr;
+               outcpsr <= next_outcpsr;
+               outspsr <= spsr;
                swp_state <= next_swp_state;
        end
 
@@ -92,87 +102,88 @@ module Memory(
                next_outbubble = inbubble;
                outstall = 1'b0;
                next_regs = regs;
+               cp_req = 1'b0;
+               cp_rnw = 1'bx;
+               cp_write = 32'hxxxxxxxx;
                offset = prev_offset;
-               next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
+               next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
                next_lsm_state = lsm_state;
                next_lsr_state = lsr_state;
                next_swp_oldval = swp_oldval;
                next_swp_state = swp_state;
                cur_reg = prev_reg;
 
-               casez(insn)
-               `DECODE_ALU_SWP: begin
-                       if(!inbubble) begin
-                               outstall = rw_wait;
-                               next_outbubble = rw_wait;
-                               busaddr = {op0[31:2], 2'b0};
-                               case(swp_state)
-                               2'b01: begin
-                                       rd_req = 1'b1;
-                                       outstall = 1'b1;
-                                       if(!rw_wait) begin
-                                               next_swp_state = 2'b10;
-                                               next_swp_oldval = rd_data;
-                                       end
-                               end
-                               2'b10: begin
-                                       wr_req = 1'b1;
-                                       wr_data = op1;
-                                       next_write_reg = 1'b1;
-                                       next_write_num = insn[15:12];
-                                       next_write_data = swp_oldval;
-                                       if(!rw_wait)
-                                               next_swp_state = 2'b01;
+               /* XXX shit not given about endianness */
+               /* TODO ldrh/strh */
+               if (flush)
+                       next_outbubble = 1'b1;
+               else casez(insn)
+               `DECODE_ALU_SWP: if(!inbubble) begin
+                       outstall = rw_wait;
+                       next_outbubble = rw_wait;
+                       busaddr = {op0[31:2], 2'b0};
+                       case(swp_state)
+                       2'b01: begin
+                               rd_req = 1'b1;
+                               outstall = 1'b1;
+                               if(!rw_wait) begin
+                                       next_swp_state = 2'b10;
+                                       next_swp_oldval = rd_data;
                                end
-                               default: begin end
-                               endcase
                        end
+                       2'b10: begin
+                               wr_req = 1'b1;
+                               wr_data = op1;
+                               next_write_reg = 1'b1;
+                               next_write_num = insn[15:12];
+                               next_write_data = swp_oldval;
+                               if(!rw_wait)
+                                       next_swp_state = 2'b01;
+                       end
+                       default: begin end
+                       endcase
                end
                `DECODE_LDRSTR_UNDEFINED: begin end
-               `DECODE_LDRSTR: begin
-                       if (!inbubble) begin
-                               next_outbubble = rw_wait;
-                               outstall = rw_wait;
-                               addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
-                               raddr = insn[24] ? op0 : addr; /* pre/post increment */
-                               busaddr = {raddr[31:2], 2'b0};
-
+               `DECODE_LDRSTR: if(!inbubble) begin
+                       next_outbubble = rw_wait;
+                       outstall = rw_wait;
+                       addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
+                       raddr = insn[24] ? op0 : addr; /* pre/post increment */
+                       busaddr = {raddr[31:2], 2'b0};
                                /* rotate to correct position */
-                               align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
-                               align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
-                               /* select byte or word */
-                               align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
-                               if(!insn[20]) begin
-                                       wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
+                       align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
+                       align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
+                       /* select byte or word */
+                       align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
+                       if(!insn[20]) begin
+                               wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
+                       end
+                       case(lsr_state)
+                       2'b01: begin
+                               rd_req = insn[20];
+                               wr_req = ~insn[20];
+                               if(insn[20]) begin
+                                       next_write_reg = 1'b1;
+                                       next_write_num = insn[15:12];
+                                       next_write_data = align_rddata;
                                end
-                               case(lsr_state)
-                               2'b01: begin
-                                       rd_req = insn[20];
-                                       wr_req = ~insn[20];
-
-                                       if(insn[20]) begin
-                                               next_write_reg = 1'b1;
-                                               next_write_num = insn[15:12];
-                                               next_write_data = align_rddata;
-                                       end
-
                                        if(insn[21]) begin
-                                               outstall = 1'b1;
-                                               if(!rw_wait)
-                                                       next_lsr_state = 2'b10;
-                                       end
-                               end
-                               2'b10: begin
-                                       next_write_reg = 1'b1;
-                                       next_write_num = insn[19:16];
-                                       next_write_data = addr;
-                                       next_lsr_state = 2'b10;
+                                       outstall = 1'b1;
+                                       if(!rw_wait)
+                                               next_lsr_state = 2'b10;
                                end
-                               default: begin end
-                               endcase
                        end
+                       2'b10: begin
+                               next_write_reg = 1'b1;
+                               next_write_num = insn[19:16];
+                               next_write_data = addr;
+                               next_lsr_state = 2'b10;
+                       end
+                       default: begin end
+                       endcase
                end
-               `DECODE_LDMSTM: begin
+               /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
+               `DECODE_LDMSTM: if(!inbubble) begin
                        outstall = rw_wait;
                        next_outbubble = rw_wait;
                        case(lsm_state)
@@ -298,6 +309,42 @@ module Memory(
                        default: begin end
                        endcase
                end
+               `DECODE_LDCSTC: if(!inbubble) begin
+                       $display("WARNING: Unimplemented LDCSTC");
+               end
+               `DECODE_CDP: if(!inbubble) begin
+                       cp_req = 1;
+                       if (cp_busy) begin
+                               outstall = 1;
+                               next_outbubble = 1;
+                       end
+                       if (!cp_ack) begin
+                               /* XXX undefined instruction trap */
+                               $display("WARNING: Possible CDP undefined instruction");
+                       end
+               end
+               `DECODE_MRCMCR: if(!inbubble) begin
+                       cp_req = 1;
+                       cp_rnw = insn[20] /* L */;
+                       if (insn[20] == 0 /* store to coprocessor */)
+                               cp_write = op0;
+                       else begin
+                               if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
+                                       next_write_reg = 1'b1;
+                                       next_write_num = insn[15:12];
+                                       next_write_data = cp_read;
+                               end else
+                                       next_outcpsr = {cp_read[31:28], cpsr[27:0]};
+                       end
+                       if (cp_busy) begin
+                               outstall = 1;
+                               next_outbubble = 1;
+                       end
+                       if (!cp_ack) begin
+                               $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
+                       end
+                       $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
+               end
                default: begin end
                endcase
        end
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