module Issue(
input clk,
- input Nrst,
+ input Nrst, /* XXX not used yet */
input stall, /* pipeline control */
input flush,
reg waiting_regs;
wire waiting = waiting_cpsr | waiting_regs;
+ initial
+ begin
+ cpsr_inflight[0] = 0;
+ cpsr_inflight[1] = 0;
+ regs_inflight[0] = 0;
+ regs_inflight[1] = 0;
+ end
+
always @(*)
begin
waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]);
end
/* Actually do the issue. */
- always @(*)
- outstall = waiting;
-
always @(posedge clk)
begin
cpsr_inflight[0] <= cpsr_inflight[1]; /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */
- cpsr_inflight[1] <= (waiting | inbubble) ? 0 : def_cpsr;
+ cpsr_inflight[1] <= ((waiting | inbubble) && condition_met) ? 0 : def_cpsr;
regs_inflight[0] <= regs_inflight[1];
- regs_inflight[1] <= (waiting | inbubble) ? 0 : def_regs;
+ regs_inflight[1] <= ((waiting | inbubble) && condition_met) ? 0 : def_regs;
outbubble <= inbubble | waiting | !condition_met;
outpc <= inpc;
outinsn <= insn;
+ outstall <= waiting && !inbubble;
end
-
endmodule