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DCache, ICache: Make cache_data a 1-D array to enable better synthesizability on...
[firearm.git] / ram.hex
diff --git a/ram.hex b/ram.hex
deleted file mode 100644 (file)
index a8160dc7c8484f9982fe2632b324ec0240636835..0000000000000000000000000000000000000000
--- a/ram.hex
+++ /dev/null
@@ -1,69 +0,0 @@
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diff --git a/ram.hex b/ram.hex
new file mode 120000 (symlink)
index 0000000000000000000000000000000000000000..6d0fcf570d97a633c5bea08c5f8355ab58d3f505
--- /dev/null
+++ b/ram.hex
@@ -0,0 +1 @@
+tests/testbench.hex
\ No newline at end of file
FireARM pipelined ARM-like CPU implementation in Verilog
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