+ wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
+ data_size = insn[22] ? 3'b001 : 3'b100;
+ case(lsr_state)
+ 4'b0001: begin
+ rd_req = insn[20] /* L */ || insn[22] /* B */;
+ wr_req = !insn[20] /* L */ && !insn[22]/* B */;
+ next_write_reg = insn[20] /* L */;
+ next_write_num = insn[15:12];
+ if(insn[20] /* L */) begin
+ next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
+ end
+ if (insn[22] /* B */ && !insn[20] /* L */) begin
+ do_rd_data_latch = 1;
+ outstall = 1'b1;
+ if (!rw_wait)
+ next_lsr_state = 4'b0010; /* XXX: One-hot, my ass. */
+ end else if(insn[21] /* W */ | !insn[24] /* P */) begin
+ outstall = 1'b1;
+ if(!rw_wait)
+ next_lsr_state = 4'b0100;
+ end
+ $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
+ end
+ 4'b0010: begin
+ $display("LDRSTR: Handling STRB");
+ outstall = 1;
+ rd_req = 0;
+ wr_req = 1;
+ next_write_reg = 0;
+ case (busaddr[1:0])
+ 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
+ 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
+ 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
+ 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
+ endcase
+ if(insn[21] /* W */ | !insn[24] /* P */) begin
+ if(!rw_wait)
+ next_lsr_state = 4'b0100;
+ end else if (!rw_wait)
+ next_lsr_state = 4'b1000;
+ end
+ 4'b0100: begin
+ outstall = 1;
+ rd_req = 0;
+ wr_req= 0;
+ next_outbubble = 0;
+ next_write_reg = 1'b1;
+ next_write_num = insn[19:16];
+ next_write_data = addr;
+ next_lsr_state = 4'b1000;
+ end
+ 4'b1000: begin
+ rd_req = 0;
+ wr_req= 0;
+ outstall = 0;
+ next_lsr_state = 4'b0001;
+ end
+ default: begin end
+ endcase
+
+ if ((lsr_state == 4'b0001) && flush) begin /* Reject it. */
+ outstall = 1'b0;
+ next_lsr_state = 4'b0001;
+ end
+ end
+ /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
+ `DECODE_LDMSTM: if(!inbubble) begin
+ outstall = rw_wait;
+ next_outbubble = rw_wait;
+ data_size = 3'b100;
+ case(lsm_state)
+ 4'b0001: begin
+// next_regs = insn[23] ? op1[15:0] : op1[0:15];
+ /** verilator can suck my dick */
+ $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
+ next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
+ op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
+ offset = 6'b0;
+ outstall = 1'b1;
+ next_lsm_state = 4'b0010;
+ end
+ 4'b0010: begin
+ rd_req = insn[20];
+ wr_req = ~insn[20];
+ casez(regs)
+ 16'b???????????????1: begin
+ cur_reg = 4'h0;
+ next_regs = {regs[15:1], 1'b0};
+ end
+ 16'b??????????????10: begin
+ cur_reg = 4'h1;
+ next_regs = {regs[15:2], 2'b0};
+ end
+ 16'b?????????????100: begin
+ cur_reg = 4'h2;
+ next_regs = {regs[15:3], 3'b0};
+ end
+ 16'b????????????1000: begin
+ cur_reg = 4'h3;
+ next_regs = {regs[15:4], 4'b0};
+ end
+ 16'b???????????10000: begin
+ cur_reg = 4'h4;
+ next_regs = {regs[15:5], 5'b0};
+ end
+ 16'b??????????100000: begin
+ cur_reg = 4'h5;
+ next_regs = {regs[15:6], 6'b0};
+ end
+ 16'b?????????1000000: begin
+ cur_reg = 4'h6;
+ next_regs = {regs[15:7], 7'b0};
+ end
+ 16'b????????10000000: begin
+ cur_reg = 4'h7;
+ next_regs = {regs[15:8], 8'b0};
+ end
+ 16'b???????100000000: begin
+ cur_reg = 4'h8;
+ next_regs = {regs[15:9], 9'b0};
+ end
+ 16'b??????1000000000: begin
+ cur_reg = 4'h9;
+ next_regs = {regs[15:10], 10'b0};
+ end
+ 16'b?????10000000000: begin
+ cur_reg = 4'hA;
+ next_regs = {regs[15:11], 11'b0};
+ end
+ 16'b????100000000000: begin
+ cur_reg = 4'hB;
+ next_regs = {regs[15:12], 12'b0};
+ end
+ 16'b???1000000000000: begin
+ cur_reg = 4'hC;
+ next_regs = {regs[15:13], 13'b0};
+ end
+ 16'b??10000000000000: begin
+ cur_reg = 4'hD;
+ next_regs = {regs[15:14], 14'b0};
+ end
+ 16'b?100000000000000: begin
+ cur_reg = 4'hE;
+ next_regs = {regs[15], 15'b0};
+ end
+ 16'b1000000000000000: begin
+ cur_reg = 4'hF;
+ next_regs = 16'b0;
+ end
+ default: begin
+ cur_reg = 4'hx;
+ next_regs = 16'b0;
+ end
+ endcase
+ cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
+ if(cur_reg == 4'hF && insn[22]) begin
+ next_outcpsr = spsr;
+ next_outcpsrup = 1;
+ end
+
+ offset = prev_offset + 6'h4;
+ offset_sel = insn[24] ? offset : prev_offset;
+ raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
+ if(insn[20]) begin
+ next_write_reg = !rw_wait;
+ next_write_num = cur_reg;
+ next_write_data = rd_data;
+ end
+ if (rw_wait) begin
+ next_regs = regs;
+ cur_reg = prev_reg; /* whoops, do this one again */
+ end
+
+ st_read = cur_reg;
+ wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
+ busaddr = raddr;
+
+ $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);