reg cache_valid [15:0];
reg [21:0] cache_tags [15:0];
reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
-
- reg [4:0] i;
+
+ integer i;
initial
for (i = 0; i < 16; i = i + 1)
begin
wire cache_hit = cache_valid[idx] && (cache_tags[idx] == tag);
+ wire [31:0] curdata = cache_data[idx][didx_word];
always @(*) begin
rw_wait = (rd_req && !cache_hit) || (wr_req && (!bus_ack || !bus_ready));
- rd_data = cache_data[idx][didx_word];
+ rd_data = curdata;
if (!rw_wait && rd_req)
$display("DCACHE: READ COMPLETE: Addr %08x, data %08x", addr, rd_data);
end
cache_fill_pos <= 0;
else if (rd_req && !cache_hit) begin
if (bus_ready && bus_ack) begin /* Started the fill, and we have data. */
+ $display("DCACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x, bus_req %d, bus_ack %d", addr, bus_addr, bus_rdata, bus_req, bus_ack);
cache_data[idx][cache_fill_pos] <= bus_rdata;
cache_fill_pos <= cache_fill_pos + 1;
if (cache_fill_pos == 15) begin /* Done? */
cache_tags[idx] <= tag;
cache_valid[idx] <= 1;
- end
+ end else
+ cache_valid[idx] <= 0;
end
end else if (wr_req && cache_hit)
- cache_data[idx][addr[5:2]] = wr_data;
+ cache_data[idx][addr[5:2]] <= wr_data;
end
endmodule