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DCache, ICache: Make cache_data a 1-D array to enable better synthesizability on...
[firearm.git] / ram.hex
diff --git a/ram.hex b/ram.hex
deleted file mode 100644 (file)
index 1a2028eebba0e520ade06f022f54f8a093ab86b0..0000000000000000000000000000000000000000
--- a/ram.hex
+++ /dev/null
@@ -1,60 +0,0 @@
-E0012011
-E0013038
-E0014058
-E0015031
-E0016071
-E0012138
-E0013158
-E0014008
-E0015028
-E0016048
-E0017068
-E00120E1
-E0013161
-E00141E1
-E0015261
-E00162E1
-E0017361
-E180F081
-E180F081
-E180F081
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
-E0000000
diff --git a/ram.hex b/ram.hex
new file mode 120000 (symlink)
index 0000000000000000000000000000000000000000..6d0fcf570d97a633c5bea08c5f8355ab58d3f505
--- /dev/null
+++ b/ram.hex
@@ -0,0 +1 @@
+tests/testbench.hex
\ No newline at end of file
FireARM pipelined ARM-like CPU implementation in Verilog
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