+ reg [31:0] reqpc;
+
+ /* Output latch logic */
+ assign rd_addr = reqpc;
+ assign rd_req = 1;
+ always @(posedge clk or negedge Nrst)
+ if (!Nrst) begin
+ bubble <= 1;
+ insn <= 0;
+ pc <= 32'h00000000;
+ end else if (!stall) begin
+ bubble <= (jmp || qjmp || rd_wait);
+ insn <= rd_data;
+ pc <= reqpc;
+ end
+
+ always @(posedge clk or negedge Nrst)
+ if (!Nrst)
+ reqpc <= 0;
+ else if (!stall && !rd_wait) begin
+ if (qjmp)
+ reqpc <= qjmppc;
+ else if (jmp)
+ reqpc <= jmppc;
+ else
+ reqpc <= reqpc + 4;
+ end