1 module MulDivDCM(input xtal, output clk);
7 BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
9 DCM_SP DCM_SP_INST (.CLKFB(GND_BIT),
17 defparam DCM_SP_INST.CLK_FEEDBACK = "NONE";
18 defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
19 defparam DCM_SP_INST.CLKFX_DIVIDE = div;
20 defparam DCM_SP_INST.CLKFX_MULTIPLY = mul;
21 defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
22 defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;
23 defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
24 defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
25 defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
26 defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
27 defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
28 defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
29 defparam DCM_SP_INST.PHASE_SHIFT = 0;
30 defparam DCM_SP_INST.STARTUP_WAIT = "TRUE";
38 output wire [2:0] r, g,
41 output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
42 inout wire [15:0] cr_DQ,
43 output wire [22:0] cr_A,
51 assign coreclk = pixclk;
52 MulDivDCM dcm31_25(xtal, pixclk);
53 defparam dcm31_25.div = 4;
54 defparam dcm31_25.mul = 2;
56 SyncGen sync(pixclk, vs, hs, x, y, border);
76 reg [16:0] rsttimer = 17'h3FFFF;
77 always @(posedge coreclk)
79 rsttimer <= 17'h3FFFF;
81 rsttimer <= rsttimer - 1;
82 assign rstact = rsttimer != 17'h0;
90 CharSet cs(cschar, csrow, csdata);
91 VideoRAM vram(pixclk, vraddr + vscroll, vrdata, coreclk, vwaddr, vwdata, vwr);
92 VDisplay dpy(pixclk, x, y, vraddr, vrdata, cschar, csrow, csdata, vcursx, vcursy, odata);
93 RXState rxsm(coreclk, vwr, vwaddr, vwdata, vscroll, vcursx, vcursy, serwr, serdata);
94 PS2 ps2(coreclk, ps2c, ps2d, sertxwr, sertxdata);
95 System sys(.clk(coreclk), .rst(rstact), .sys_odata({serwr, serdata}), .sys_idata({ps2_hasd, ps2_d}), .sys_tookdata(tookdata),
108 always @(posedge coreclk)
110 {ps2_hasd, ps2_d} <= {1'b1, sertxdata};
112 {ps2_hasd, ps2_d} <= {1'b0, 8'hxxxxxxxx};
114 wire [7:0] red, green, blue;
115 assign r = (odata ? 3'b111 : 0) | (x[8:7] ^ y[7:6]);
116 assign g = (odata ? 3'b111 : 0) | (x[7:6] ^ y[8:7]);
117 assign b = (odata ? 2'b11 : 0) | (x[8 ] ^ y[8 ]);
123 output reg [11:0] x, y,
126 parameter XRES = 640;
127 parameter XFPORCH = 16;
128 parameter XSYNC = 96;
129 parameter XBPORCH = 48;
131 parameter YRES = 480;
132 parameter YFPORCH = 10;
134 parameter YBPORCH = 29;
136 always @(posedge pixclk)
138 if (x >= (XRES + XFPORCH + XSYNC + XBPORCH))
140 if (y >= (YRES + YFPORCH + YSYNC + YBPORCH))
147 hs <= (x >= (XRES + XFPORCH)) && (x < (XRES + XFPORCH + XSYNC));
148 vs <= (y >= (YRES + YFPORCH)) && (y < (YRES + YFPORCH + YSYNC));
149 border <= (x > XRES) || (y > YRES);
156 output wire [7:0] data);
158 reg [7:0] rom [(256 * 8 - 1):0];
161 $readmemb("ibmpc1.mem", rom);
163 assign data = rom[{char, row}];
169 output reg [7:0] rdata,
175 reg [7:0] ram [2047 : 0];
177 always @(posedge pixclk)
180 always @(posedge wclk)
189 output wire [10:0] raddr,
191 output wire [7:0] cschar,
192 output wire [2:0] csrow,
198 wire [7:0] col = x[11:3];
199 wire [5:0] row = y[10:4];
203 assign raddr = ({row,4'b0} + {row,6'b0} + {4'h0,col});
204 assign cschar = rchar;
205 assign csrow = y[3:1];
207 reg [23:0] blinktime = 0;
209 always @(posedge pixclk) blinktime <= blinktime + 1;
211 wire curssel = (cursx == col) && (cursy == row) && blinktime[23];
213 always @(posedge pixclk)
216 always @(posedge pixclk)
217 data = ((xdly < 80 * 8) && (y < 25 * 16)) ? (csdata[7 - xdly[2:0]] ^ curssel) : 0;
223 output reg [10:0] vwaddr = 0,
224 output reg [7:0] vwdata = 0,
225 output reg [10:0] vscroll = 0,
226 output wire [6:0] vcursx,
227 output wire [4:0] vcursy,
229 input [7:0] serdata);
231 parameter STATE_IDLE = 4'b0000;
232 parameter STATE_NEWLINE = 4'b0001;
233 parameter STATE_CLEAR = 4'b0010;
235 reg [3:0] state = STATE_CLEAR;
243 reg [10:0] clearstart = 0;
244 reg [10:0] clearend = 11'b11111111111;
246 always @(posedge clk25)
248 STATE_IDLE: if (serwr) begin
249 if (serdata == 8'h0A) begin
250 state <= STATE_NEWLINE;
253 end else if (serdata == 8'h0D) begin
256 end else if (serdata == 8'h0C) begin
258 clearend <= 11'b11111111111;
262 state <= STATE_CLEAR;
263 end else if (serdata == 8'h08) begin
269 vwaddr <= ({y,4'b0} + {y,6'b0} + {4'h0,x}) + vscroll;
273 state <= STATE_NEWLINE;
282 vscroll <= vscroll + 80;
283 clearstart <= (25 * 80) + vscroll;
284 clearend <= (26*80) + vscroll;
285 state <= STATE_CLEAR;
294 vwaddr <= clearstart;
296 clearstart <= clearstart + 1;
297 if (clearstart == clearend)
308 output reg [7:0] data
311 reg [3:0] bitcount = 0;
313 reg keyarrow = 0, keyup = 0, parity = 0;
316 /* Clock debouncing */
318 reg [6:0] debounce = 0;
320 reg [11:0] resetcountdown = 0;
322 reg [6:0] unshiftedrom [127:0]; initial $readmemh("scancodes.unshifted.hex", unshiftedrom);
323 reg [6:0] shiftedrom [127:0]; initial $readmemh("scancodes.shifted.hex", shiftedrom);
327 reg mod_capslock = 0;
328 wire mod_shifted = (mod_lshift | mod_rshift) ^ mod_capslock;
333 always @(posedge pixclk) begin
334 if (inclk != lastinclk) begin
337 resetcountdown <= 12'b111111111111;
338 end else if (debounce == 0) begin
340 resetcountdown <= resetcountdown - 1;
342 debounce <= debounce + 1;
344 if (nd ^ lastnd) begin
351 always @(negedge fixedclk) begin
352 if (resetcountdown == 0)
354 else if (bitcount == 10) begin
356 if(parity != (^ key)) begin
360 8'hxx: keyarrow <= 0;
368 8'h12: mod_lshift <= 0;
369 8'h59: mod_rshift <= 0;
371 // handle this? I don't fucking know
375 8'hE0: keyarrow <= 1; // handle these? I don't fucking know
377 8'h12: mod_lshift <= 1;
378 8'h59: mod_rshift <= 1;
379 8'h14: mod_capslock <= ~mod_capslock;
380 8'b0xxxxxxx: begin nd <= ~nd; data <= mod_shifted ? shiftedrom[key] : unshiftedrom[key]; end
381 8'b1xxxxxxx: begin /* AAAAAAASSSSSSSS */ end
391 bitcount <= bitcount + 1;