Merge branch 'master' of nyus.joshuawise.com:/git/firearm
[firearm.git] / Memory.v
1 `include "ARM_Constants.v"
2
3 module Memory(
4         input clk,
5         input Nrst,
6
7         /* bus interface */
8         output reg [31:0] busaddr,
9         output reg rd_req,
10         output reg wr_req,
11         input rw_wait,
12         output reg [31:0] wr_data,
13         input [31:0] rd_data,
14
15         /* regfile interface */
16         output reg [3:0] st_read,
17         input [31:0] st_data,
18         
19         /* Coprocessor interface */
20         output reg cp_req,
21         input cp_ack,
22         input cp_busy,
23         output cp_rnw,  /* 1 = read from CP, 0 = write to CP */
24         input [31:0] cp_read,
25         output reg [31:0] cp_write,
26         
27         /* stage inputs */
28         input inbubble,
29         input [31:0] pc,
30         input [31:0] insn,
31         input [31:0] op0,
32         input [31:0] op1,
33         input [31:0] op2,
34         input [31:0] spsr,
35         input [31:0] cpsr,
36         input write_reg,
37         input [3:0] write_num,
38         input [31:0] write_data,
39
40         /* outputs */
41         output reg outstall,
42         output reg outbubble,
43         output reg [31:0] outpc,
44         output reg [31:0] outinsn,
45         output reg out_write_reg = 1'b0,
46         output reg [3:0] out_write_num = 4'bxxxx,
47         output reg [31:0] out_write_data = 32'hxxxxxxxx,
48         output reg [31:0] out_spsr = 32'hxxxxxxxx,
49         output reg [31:0] out_cpsr = 32'hxxxxxxxx
50         );
51
52         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
53         reg [31:0] prevaddr;
54         reg [3:0] next_regsel, cur_reg, prev_reg;
55         reg next_writeback;
56
57         wire next_outbubble;    
58         wire next_write_reg;
59         wire [3:0] next_write_num;
60         wire [31:0] next_write_data;
61
62         reg [1:0] lsr_state = 2'b01, next_lsr_state;
63         reg [31:0] align_s1, align_s2, align_rddata;
64
65         reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
66         reg [31:0] lsrh_rddata;
67         reg [15:0] lsrh_rddata_s1;
68         reg [7:0] lsrh_rddata_s2;
69
70         reg [15:0] regs, next_regs;
71         reg [2:0] lsm_state = 3'b001, next_lsm_state;
72         reg [5:0] offset, prev_offset, offset_sel;
73
74         reg [31:0] swp_oldval, next_swp_oldval;
75         reg [1:0] swp_state = 2'b01, next_swp_state;
76
77         always @(posedge clk)
78         begin
79                 outpc <= pc;
80                 outinsn <= insn;
81                 outbubble <= next_outbubble;
82                 out_write_reg <= next_write_reg;
83                 out_write_num <= next_write_num;
84                 out_write_data <= next_write_data;
85                 regs <= next_regs;
86                 prev_reg <= cur_reg;
87                 prev_offset <= offset;
88                 prev_raddr <= raddr;
89                 out_cpsr <= next_outcpsr;
90                 out_spsr <= spsr;
91                 swp_state <= next_swp_state;
92                 lsm_state <= next_lsm_state;
93                 lsr_state <= next_lsr_state;
94                 lsrh_state <= next_lsrh_state;
95                 prevaddr <= addr;
96         end
97
98         always @(*)
99         begin
100                 addr = prevaddr;
101                 raddr = 32'hxxxxxxxx;
102                 rd_req = 1'b0;
103                 wr_req = 1'b0;
104                 wr_data = 32'hxxxxxxxx;
105                 busaddr = 32'hxxxxxxxx;
106                 outstall = 1'b0;
107                 next_write_reg = write_reg;
108                 next_write_num = write_num;
109                 next_write_data = write_data;
110                 next_outbubble = inbubble;
111                 outstall = 1'b0;
112                 next_regs = regs;
113                 cp_req = 1'b0;
114                 cp_rnw = 1'bx;
115                 cp_write = 32'hxxxxxxxx;
116                 offset = prev_offset;
117                 next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
118                 lsrh_rddata = 32'hxxxxxxxx;
119                 next_lsm_state = lsm_state;
120                 next_lsr_state = lsr_state;
121                 next_lsrh_state = lsrh_state;
122                 next_swp_oldval = swp_oldval;
123                 next_swp_state = swp_state;
124                 cur_reg = prev_reg;
125
126                 /* XXX shit not given about endianness */
127                 /* TODO ldrh/strh */
128                 casez(insn)
129                 `DECODE_ALU_SWP: if(!inbubble) begin
130                         outstall = rw_wait;
131                         next_outbubble = rw_wait;
132                         busaddr = {op0[31:2], 2'b0};
133                         case(swp_state)
134                         2'b01: begin
135                                 rd_req = 1'b1;
136                                 outstall = 1'b1;
137                                 if(!rw_wait) begin
138                                         next_swp_state = 2'b10;
139                                         next_swp_oldval = rd_data;
140                                 end
141                         end
142                         2'b10: begin
143                                 wr_req = 1'b1;
144                                 wr_data = op1;
145                                 next_write_reg = 1'b1;
146                                 next_write_num = insn[15:12];
147                                 next_write_data = swp_oldval;
148                                 if(!rw_wait)
149                                         next_swp_state = 2'b01;
150                         end
151                         default: begin end
152                         endcase
153                 end
154                 `DECODE_ALU_HDATA_REG,
155                 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
156                         next_outbubble = rw_wait;
157                         outstall = rw_wait;
158                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
159                         raddr = insn[24] ? op0 : addr; /* pre/post increment */
160                         busaddr = raddr;
161                         /* rotate to correct position */
162                         case(insn[6:5])
163                         2'b00: begin end /* swp */
164                         2'b01: begin /* unsigned half */
165                                 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
166                                 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
167                         end
168                         2'b10: begin /* signed byte */
169                                 wr_data = {4{op2[7:0]}};
170                                 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
171                                 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
172                                 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
173                         end
174                         2'b11: begin /* signed half */
175                                 wr_data = {2{op2[15:0]}};
176                                 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
177                         end
178                         endcase
179
180                         case(lsrh_state)
181                         2'b01: begin
182                                 rd_req = insn[20];
183                                 wr_req = ~insn[20];
184                                 next_write_num = insn[15:12];
185                                 next_write_data = lsrh_rddata;
186                                 if(insn[20]) begin
187                                         next_write_reg = 1'b1;
188                                 end
189                                 if(insn[21] | !insn[24]) begin
190                                         outstall = 1'b1;
191                                         if(!rw_wait)
192                                                 next_lsrh_state = 2'b10;
193                                 end
194                         end
195                         2'b10: begin
196                                 next_write_reg = 1'b1;
197                                 next_write_num = insn[19:16];
198                                 next_write_data = addr;
199                                 next_lsrh_state = 2'b10;
200                         end
201                         default: begin end
202                         endcase
203                 end
204                 `DECODE_LDRSTR_UNDEFINED: begin end
205                 `DECODE_LDRSTR: if(!inbubble) begin
206                         next_outbubble = rw_wait;
207                         outstall = rw_wait;
208                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
209                         raddr = insn[24] ? op0 : addr; /* pre/post increment */
210                         busaddr = raddr;
211                         /* rotate to correct position */
212                         align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
213                         align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
214                         /* select byte or word */
215                         align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
216                         wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
217                         case(lsr_state)
218                         2'b01: begin
219                                 rd_req = insn[20];
220                                 wr_req = ~insn[20];
221                                 next_write_reg = 1'b1;
222                                 next_write_num = insn[15:12];
223                                 if(insn[20]) begin
224                                         next_write_data = align_rddata;
225                                 end
226                                 if(insn[21] | !insn[24]) begin
227                                         outstall = 1'b1;
228                                         if(!rw_wait)
229                                                 next_lsr_state = 2'b10;
230                                 end
231                         end
232                         2'b10: begin
233                                 next_write_reg = 1'b1;
234                                 next_write_num = insn[19:16];
235                                 next_write_data = addr;
236                                 next_lsr_state = 2'b10;
237                         end
238                         default: begin end
239                         endcase
240                 end
241                 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
242                 `DECODE_LDMSTM: if(!inbubble) begin
243                         outstall = rw_wait;
244                         next_outbubble = rw_wait;
245                         case(lsm_state)
246                         3'b001: begin
247 //                              next_regs = insn[23] ? op1[15:0] : op1[0:15];
248                                 /** verilator can suck my dick */
249                                 next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
250                                                                     op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
251                                 offset = 6'b0;
252                                 outstall = 1'b1;
253                                 next_lsm_state = 3'b010;
254                         end
255                         3'b010: begin
256                                 rd_req = insn[20];
257                                 wr_req = ~insn[20];
258                                 casez(regs)
259                                 16'b???????????????1: begin
260                                         cur_reg = 4'h0;
261                                         next_regs = {regs[15:1], 1'b0};
262                                 end
263                                 16'b??????????????10: begin
264                                         cur_reg = 4'h1;
265                                         next_regs = {regs[15:2], 2'b0};
266                                 end
267                                 16'b?????????????100: begin
268                                         cur_reg = 4'h2;
269                                         next_regs = {regs[15:3], 3'b0};
270                                 end
271                                 16'b????????????1000: begin
272                                         cur_reg = 4'h3;
273                                         next_regs = {regs[15:4], 4'b0};
274                                 end
275                                 16'b???????????10000: begin
276                                         cur_reg = 4'h4;
277                                         next_regs = {regs[15:5], 5'b0};
278                                 end
279                                 16'b??????????100000: begin
280                                         cur_reg = 4'h5;
281                                         next_regs = {regs[15:6], 6'b0};
282                                 end
283                                 16'b?????????1000000: begin
284                                         cur_reg = 4'h6;
285                                         next_regs = {regs[15:7], 7'b0};
286                                 end
287                                 16'b????????10000000: begin
288                                         cur_reg = 4'h7;
289                                         next_regs = {regs[15:8], 8'b0};
290                                 end
291                                 16'b???????100000000: begin
292                                         cur_reg = 4'h8;
293                                         next_regs = {regs[15:9], 9'b0};
294                                 end
295                                 16'b??????1000000000: begin
296                                         cur_reg = 4'h9;
297                                         next_regs = {regs[15:10], 10'b0};
298                                 end
299                                 16'b?????10000000000: begin
300                                         cur_reg = 4'hA;
301                                         next_regs = {regs[15:11], 11'b0};
302                                 end
303                                 16'b????100000000000: begin
304                                         cur_reg = 4'hB;
305                                         next_regs = {regs[15:12], 12'b0};
306                                 end
307                                 16'b???1000000000000: begin
308                                         cur_reg = 4'hC;
309                                         next_regs = {regs[15:13], 13'b0};
310                                 end
311                                 16'b??10000000000000: begin
312                                         cur_reg = 4'hD;
313                                         next_regs = {regs[15:14], 14'b0};
314                                 end
315                                 16'b?100000000000000: begin
316                                         cur_reg = 4'hE;
317                                         next_regs = {regs[15], 15'b0};
318                                 end
319                                 16'b1000000000000000: begin
320                                         cur_reg = 4'hF;
321                                         next_regs = 16'b0;
322                                 end
323                                 default: begin
324                                         cur_reg = 4'hx;
325                                         next_regs = 16'b0;
326                                 end
327                                 endcase
328                                 cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
329                                 if(cur_reg == 4'hF && insn[22]) begin
330                                         next_outcpsr = spsr;
331                                 end
332
333                                 if(rw_wait) begin
334                                         next_regs = regs;
335                                         cur_reg = prev_reg;
336                                         raddr = prev_raddr;
337                                 end
338                                 else begin
339                                         offset = prev_offset + 6'h4;
340                                         offset_sel = insn[24] ? offset : prev_offset;
341                                         raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
342                                         if(insn[20]) begin
343                                                 next_write_reg = 1'b1;
344                                                 next_write_num = cur_reg;
345                                                 next_write_data = rd_data;
346                                         end
347                                 end
348
349                                 st_read = cur_reg;
350                                 wr_data = st_data;
351                                 busaddr = raddr;
352
353                                 outstall = 1'b1;
354
355                                 if(next_regs == 16'b0) begin
356                                         next_lsm_state = 3'b100;
357                                 end
358                         end
359                         3'b100: begin
360                                 next_write_reg = 1'b1;
361                                 next_write_num = insn[19:16];
362                                 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
363                                 next_lsm_state = 3'b001;
364                         end
365                         default: begin end
366                         endcase
367                 end
368                 `DECODE_LDCSTC: if(!inbubble) begin
369                         $display("WARNING: Unimplemented LDCSTC");
370                 end
371                 `DECODE_CDP: if(!inbubble) begin
372                         cp_req = 1;
373                         if (cp_busy) begin
374                                 outstall = 1;
375                                 next_outbubble = 1;
376                         end
377                         if (!cp_ack) begin
378                                 /* XXX undefined instruction trap */
379                                 $display("WARNING: Possible CDP undefined instruction");
380                         end
381                 end
382                 `DECODE_MRCMCR: if(!inbubble) begin
383                         cp_req = 1;
384                         cp_rnw = insn[20] /* L */;
385                         if (insn[20] == 0 /* store to coprocessor */)
386                                 cp_write = op0;
387                         else begin
388                                 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
389                                         next_write_reg = 1'b1;
390                                         next_write_num = insn[15:12];
391                                         next_write_data = cp_read;
392                                 end else
393                                         next_outcpsr = {cp_read[31:28], cpsr[27:0]};
394                         end
395                         if (cp_busy) begin
396                                 outstall = 1;
397                                 next_outbubble = 1;
398                         end
399                         if (!cp_ack) begin
400                                 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
401                         end
402                         $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
403                 end
404                 default: begin end
405                 endcase
406         end
407 endmodule
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