with more reg
[firearm.git] / Decode.v
1 `include "ARM_Constants.v"
2
3 module Decode(
4         input clk,
5         input [31:0] insn,
6         input [31:0] inpc,
7         input [31:0] incpsr,
8         output reg [31:0] op0,
9         output reg [31:0] op1,
10         output reg [31:0] op2,
11         output reg carry,
12
13         output reg [3:0] read_0,
14         output reg [3:0] read_1,
15         output reg [3:0] read_2,
16         input [31:0] rdata_0,
17         input [31:0] rdata_1,
18         input [31:0] rdata_2
19         );
20
21         wire [31:0] regs0, regs1, regs2;
22         reg [31:0] rpc;
23         reg [31:0] op0_out, op1_out, op2_out;
24         reg carry_out;
25
26         /* shifter stuff */
27         wire [31:0] shift_oper;
28         wire [31:0] shift_res;
29         wire shift_cflag_out;
30         wire [31:0] rotate_res;
31
32         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
33         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
34         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
35
36         IREALLYHATEARMSHIFT blowme(.insn(insn),
37                                    .operand(regs1),
38                                    .reg_amt(regs2),
39                                    .cflag_in(incpsr[`CPSR_C]),
40                                    .res(shift_res),
41                                    .cflag_out(shift_cflag_out));
42
43         SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
44                               .amt(insn[11:8]),
45                               .res(rotate_res));
46
47         always @(*)
48                 casez (insn)
49                 32'b????000000??????????????1001????,   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
50 //              32'b????00001???????????????1001????,   /* Multiply long */
51                 32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
52                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
53                 32'b????00?10?1010001111????????????,   /* MSR (Transfer register or immediate to PSR, flag bits only) */
54                 32'b????00010?00????????00001001????,   /* Atomic swap */
55                 32'b????000100101111111111110001????,   /* Branch and exchange */
56                 32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
57                 32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
58                 32'b????011????????????????????1????,   /* Undefined. I hate ARM */
59                 32'b????01??????????????????????????,   /* Single data transfer */
60                 32'b????100?????????????????????????,   /* Block data transfer */
61                 32'b????101?????????????????????????,   /* Branch */
62                 32'b????110?????????????????????????,   /* Coprocessor data transfer */
63                 32'b????1110???????????????????0????,   /* Coprocessor data op */
64                 32'b????1110???????????????????1????,   /* Coprocessor register transfer */
65                 32'b????1111????????????????????????:   /* SWI */
66                         rpc = inpc - 8;
67                 32'b????00??????????????????????????:   /* ALU */
68                         rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
69                 default:                                /* X everything else out */
70                         rpc = 32'hxxxxxxxx;
71                 endcase
72
73         always @(*) begin
74                 read_0 = 4'hx;
75                 read_1 = 4'hx;
76                 read_2 = 4'hx;
77                 
78                 casez (insn)
79                 32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
80                 begin
81                         read_0 = insn[15:12]; /* Rn */
82                         read_1 = insn[3:0];   /* Rm */
83                         read_2 = insn[11:8];  /* Rs */
84                 end
85 //              32'b????00001???????????????1001????,   /* Multiply long */
86 //                      read_0 = insn[11:8]; /* Rn */
87 //                      read_1 = insn[3:0];   /* Rm */
88 //                      read_2 = 4'b0;       /* anyus */
89                 32'b????00010?001111????000000000000:   /* MRS (Transfer PSR to register) */
90                 begin end
91                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
92                 32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
93                         read_0 = insn[3:0];     /* Rm */
94                 32'b????00??????????????????????????:   /* ALU */
95                 begin
96                         read_0 = insn[19:16]; /* Rn */
97                         read_1 = insn[3:0];   /* Rm */
98                         read_2 = insn[11:8];  /* Rs for shift */
99                 end
100                 32'b????00010?00????????00001001????:   /* Atomic swap */
101                 begin
102                         read_0 = insn[19:16]; /* Rn */
103                         read_1 = insn[3:0];   /* Rm */
104                 end
105                 32'b????000100101111111111110001????:   /* Branch and exchange */
106                         read_0 = insn[3:0];   /* Rn */
107                 32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
108                 begin
109                         read_0 = insn[19:16];
110                         read_1 = insn[3:0];
111                 end
112                 32'b????000??1??????????00001??1????:   /* Halfword transfer - immediate offset */
113                 begin
114                         read_0 = insn[19:16];
115                 end
116                 32'b????011????????????????????1????:   /* Undefined. I hate ARM */
117                 begin end
118                 32'b????01??????????????????????????:   /* Single data transfer */
119                 begin
120                         read_0 = insn[19:16]; /* Rn */
121                         read_1 = insn[3:0];   /* Rm */
122                 end
123                 32'b????100?????????????????????????:   /* Block data transfer */
124                         read_0 = insn[19:16];
125                 32'b????101?????????????????????????:   /* Branch */
126                 begin end
127                 32'b????110?????????????????????????:   /* Coprocessor data transfer */
128                         read_0 = insn[19:16];
129                 32'b????1110???????????????????0????:   /* Coprocessor data op */
130                 begin end
131                 32'b????1110???????????????????1????:   /* Coprocessor register transfer */
132                         read_0 = insn[15:12];
133                 32'b????1111????????????????????????:   /* SWI */
134                 begin end
135                 default:
136                         $display("Undecoded instruction");
137                 endcase
138         end
139         
140         always @(*) begin
141                 op0_out = 32'hxxxxxxxx;
142                 op1_out = 32'hxxxxxxxx;
143                 op2_out = 32'hxxxxxxxx;
144                 carry_out = 1'bx;
145                 casez (insn)
146                 32'b????000000??????????????1001????: begin /* Multiply */
147                         op0_out = regs0;
148                         op1_out = regs1;
149                         op2_out = regs2;
150                 end
151 //              32'b????00001???????????????1001????: begin /* Multiply long */
152 //                      op1_res = regs1;
153 //              end
154                 32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
155                 end
156                 32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
157                         op0_out = regs0;
158                 end
159                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
160                         if(insn[25]) begin     /* the constant case */
161                                 op0_out = rotate_res;
162                         end else begin
163                                 op0_out = regs0;
164                         end
165                 end
166                 32'b????00??????????????????????????: begin /* ALU */
167                         op0_out = regs0;
168                         if(insn[25]) begin     /* the constant case */
169                                 carry_out = incpsr[`CPSR_C];
170                                 op1_out = rotate_res;
171                         end else begin
172                                 carry_out = shift_cflag_out;
173                                 op1_out = shift_res;
174                         end
175                 end
176                 32'b????00010?00????????00001001????: begin /* Atomic swap */
177                         op0_out = regs0;
178                         op1_out = regs1;
179                 end
180                 32'b????000100101111111111110001????: begin /* Branch and exchange */
181                         op0_out = regs0;
182                 end
183                 32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
184                         op0_out = regs0;
185                         op1_out = regs1;
186                 end
187                 32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
188                         op0_out = regs0;
189                         op1_out = {24'b0, insn[11:8], insn[3:0]};
190                 end
191                 32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
192                         /* eat shit */
193                 end
194                 32'b????01??????????????????????????: begin /* Single data transfer */
195                         op0_out = regs0;
196                         if(insn[25]) begin
197                                 op1_out = {20'b0, insn[11:0]};
198                                 carry_out = incpsr[`CPSR_C];
199                         end else begin
200                                 op1_out = shift_res;
201                                 carry_out = shift_cflag_out;
202                         end
203                 end
204                 32'b????100?????????????????????????: begin /* Block data transfer */
205                         op0_out = regs0;
206                         op1_out = {16'b0, insn[15:0]};
207                 end
208                 32'b????101?????????????????????????: begin /* Branch */
209                         op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
210                 end
211                 32'b????110?????????????????????????: begin /* Coprocessor data transfer */
212                         op0_out = regs0;
213                         op1_out = {24'b0, insn[7:0]};
214                 end
215                 32'b????1110???????????????????0????: begin /* Coprocessor data op */
216                 end
217                 32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
218                         op0_out = regs0;
219                 end
220                 32'b????1111????????????????????????: begin /* SWI */
221                 end
222                 default: begin end
223                 endcase
224         end
225
226         always @ (posedge clk) begin
227                 op0 <= op0_out;   /* Rn - always */
228                 op1 <= op1_out; /* 'operand 2' - Rm */
229                 op2 <= op2_out;   /* thirdedge - Rs */
230                 carry <= carry_out;
231         end
232
233 endmodule
234
235 module IREALLYHATEARMSHIFT(
236         input [31:0] insn,
237         input [31:0] operand,
238         input [31:0] reg_amt,
239         input cflag_in,
240         output reg [31:0] res,
241         output reg cflag_out
242 );
243         wire [5:0] shift_amt;
244         reg rshift_cout, is_arith, is_rot;
245         reg [31:0] rshift_res;
246
247         assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
248                                    : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
249
250         SuckLessShifter biteme(.oper(operand),
251                                .carryin(cflag_in),
252                                .amt(shift_amt),
253                                .is_arith(is_arith),
254                                .is_rot(is_rot),
255                                .res(rshift_res),
256                                .carryout(rshift_cout));
257
258         always @(*)
259                 case (insn[6:5])
260                 `SHIFT_LSL: begin
261                         /* meaningless */
262                         is_rot = 1'b0;
263                         is_arith = 1'b0;
264                 end
265                 `SHIFT_LSR: begin
266                         is_rot = 1'b0;
267                         is_arith = 1'b0;
268                 end
269                 `SHIFT_ASR: begin
270                         is_rot = 1'b0;
271                         is_arith = 1'b1;
272                 end
273                 `SHIFT_ROR: begin
274                         is_rot = 1'b1;
275                         is_arith = 1'b0;
276                 end
277                 endcase
278
279         always @(*)
280                 case (insn[6:5]) /* shift type */
281                 `SHIFT_LSL:
282                         {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
283                 `SHIFT_LSR: begin
284                         res = rshift_res;
285                         cflag_out = rshift_cout;
286                 end
287                 `SHIFT_ASR: begin
288                         res = rshift_res;
289                         cflag_out = rshift_cout;
290                 end
291                 `SHIFT_ROR: begin
292                         if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
293                                 res = {cflag_in, operand[31:1]};
294                                 cflag_out = operand[0];
295                         end else begin
296                                 res = rshift_res;
297                                 cflag_out = rshift_cout;
298                         end
299                 end
300                 endcase
301 endmodule
302
303 module SuckLessShifter(
304         input [31:0] oper,
305         input carryin,
306         input [5:0] amt,
307         input is_arith,
308         input is_rot,
309         output [31:0] res,
310         output carryout
311 );
312
313         wire [32:0] stage1, stage2, stage3, stage4, stage5;
314
315         wire pushbits = is_arith & oper[31];
316
317         /* do a barrel shift */
318         assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
319         assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
320         assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
321         assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
322         assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
323         assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
324
325 endmodule
326
327 module SuckLessRotator(
328         input [31:0] oper,
329         input [3:0] amt,
330         output [31:0] res
331 );
332
333         wire [31:0] stage1, stage2, stage3;
334         assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
335         assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
336         assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
337         assign res    = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
338
339 endmodule
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