1 `include "ARM_Constants.v"
10 output reg [31:0] busaddr,
14 output reg [31:0] wr_data,
16 output reg [2:0] data_size,
18 /* regfile interface */
19 output reg [3:0] st_read,
22 /* Coprocessor interface */
26 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
28 output reg [31:0] cp_write,
41 input [3:0] write_num,
42 input [31:0] write_data,
47 output reg [31:0] outpc,
48 output reg [31:0] outinsn,
49 output reg out_write_reg = 1'b0,
50 output reg [3:0] out_write_num = 4'bxxxx,
51 output reg [31:0] out_write_data = 32'hxxxxxxxx,
52 output reg [31:0] outspsr = 32'hxxxxxxxx,
53 output reg [31:0] outcpsr = 32'hxxxxxxxx,
54 output reg outcpsrup = 1'hx
57 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
60 reg [3:0] next_regsel, cur_reg, prev_reg;
65 reg [3:0] next_write_num;
66 reg [31:0] next_write_data;
68 reg [3:0] lsr_state = 4'b0001, next_lsr_state;
69 reg [31:0] align_s1, align_s2, align_rddata;
71 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
72 reg [31:0] lsrh_rddata;
73 reg [15:0] lsrh_rddata_s1;
74 reg [7:0] lsrh_rddata_s2;
76 reg [15:0] regs, next_regs;
77 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
78 reg [5:0] offset, prev_offset, offset_sel;
80 reg [31:0] swp_oldval, next_swp_oldval;
81 reg [1:0] swp_state = 2'b01, next_swp_state;
84 reg [31:0] rd_data_latch = 32'hxxxxxxxx;
90 outbubble <= next_outbubble;
91 out_write_reg <= next_write_reg;
92 out_write_num <= next_write_num;
93 out_write_data <= next_write_data;
97 prev_offset <= offset;
99 outcpsr <= next_outcpsr;
101 outcpsrup <= next_outcpsrup;
102 swp_state <= next_swp_state;
103 lsm_state <= next_lsm_state;
104 lsr_state <= next_lsr_state;
105 lsrh_state <= next_lsrh_state;
106 if (do_rd_data_latch)
107 rd_data_latch <= rd_data;
111 reg delayedflush = 0;
112 always @(posedge clk)
113 if (flush && outstall /* halp! I can't do it now, maybe later? */)
115 else if (!outstall /* anything has been handled this time around */)
121 raddr = 32'hxxxxxxxx;
124 wr_data = 32'hxxxxxxxx;
125 busaddr = 32'hxxxxxxxx;
128 do_rd_data_latch = 0;
129 next_write_reg = write_reg;
130 next_write_num = write_num;
131 next_write_data = write_data;
132 next_outbubble = inbubble;
136 cp_write = 32'hxxxxxxxx;
137 offset = prev_offset;
138 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
139 next_outcpsrup = cpsrup;
140 lsrh_rddata = 32'hxxxxxxxx;
141 lsrh_rddata_s1 = 16'hxxxx;
142 lsrh_rddata_s2 = 8'hxx;
143 next_lsm_state = lsm_state;
144 next_lsr_state = lsr_state;
145 next_lsrh_state = lsrh_state;
146 next_swp_oldval = swp_oldval;
147 next_swp_state = swp_state;
150 /* XXX shit not given about endianness */
152 `DECODE_ALU_SWP: if(!inbubble) begin
154 next_outbubble = rw_wait;
155 busaddr = {op0[31:2], 2'b0};
156 data_size = insn[22] ? 3'b001 : 3'b100;
162 next_swp_state = 2'b10;
163 next_swp_oldval = rd_data;
165 $display("SWP: read stage");
169 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
170 next_write_reg = 1'b1;
171 next_write_num = insn[15:12];
172 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
174 next_swp_state = 2'b01;
175 $display("SWP: write stage");
180 `DECODE_ALU_MULT: begin end
181 `DECODE_ALU_HDATA_REG,
182 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
183 next_outbubble = rw_wait;
185 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
186 raddr = insn[24] ? op0 : addr; /* pre/post increment */
188 /* rotate to correct position */
190 2'b00: begin end /* swp */
191 2'b01: begin /* unsigned half */
192 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
194 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
196 2'b10: begin /* signed byte */
197 wr_data = {4{op2[7:0]}};
199 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
200 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
201 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
203 2'b11: begin /* signed half */
204 wr_data = {2{op2[15:0]}};
206 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
214 next_write_num = insn[15:12];
215 next_write_data = lsrh_rddata;
217 next_write_reg = 1'b1;
219 if(insn[21] | !insn[24]) begin
222 next_lsrh_state = 3'b010;
224 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
227 next_outbubble = 1'b0;
228 next_write_reg = 1'b1;
229 next_write_num = insn[19:16];
230 next_write_data = addr;
231 next_lsrh_state = 3'b100;
235 next_lsrh_state = 3'b001;
240 if ((lsrh_state == 3'b001) && flush) begin /* Reject it. */
242 next_lsrh_state = 3'b001;
245 `DECODE_LDRSTR_UNDEFINED: begin end
246 `DECODE_LDRSTR: if(!inbubble) begin
247 next_outbubble = rw_wait;
249 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
250 raddr = insn[24] ? addr : op0; /* pre/post increment */
252 /* rotate to correct position */
253 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
254 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
255 /* select byte or word */
256 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
257 wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
258 data_size = insn[22] ? 3'b001 : 3'b100;
261 rd_req = insn[20] /* L */ || insn[22] /* B */;
262 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
263 next_write_reg = insn[20] /* L */;
264 next_write_num = insn[15:12];
265 if(insn[20] /* L */) begin
266 next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
268 if (insn[22] /* B */ && !insn[20] /* L */) begin
269 do_rd_data_latch = 1;
272 next_lsr_state = 4'b0010; /* XXX: One-hot, my ass. */
273 end else if(insn[21] /* W */ | !insn[24] /* P */) begin
276 next_lsr_state = 4'b0100;
278 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
281 $display("LDRSTR: Handling STRB");
287 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
288 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
289 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
290 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
292 if(insn[21] /* W */ | !insn[24] /* P */) begin
294 next_lsr_state = 4'b0100;
295 end else if (!rw_wait)
296 next_lsr_state = 4'b1000;
303 next_write_reg = 1'b1;
304 next_write_num = insn[19:16];
305 next_write_data = addr;
306 next_lsr_state = 4'b1000;
312 next_lsr_state = 4'b0001;
317 if ((lsr_state == 4'b0001) && flush) begin /* Reject it. */
319 next_lsr_state = 4'b0001;
322 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
323 `DECODE_LDMSTM: if(!inbubble) begin
325 next_outbubble = rw_wait;
329 // next_regs = insn[23] ? op1[15:0] : op1[0:15];
330 /** verilator can suck my dick */
331 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
332 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
333 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
336 next_lsm_state = 4'b0010;
342 16'b???????????????1: begin
344 next_regs = {regs[15:1], 1'b0};
346 16'b??????????????10: begin
348 next_regs = {regs[15:2], 2'b0};
350 16'b?????????????100: begin
352 next_regs = {regs[15:3], 3'b0};
354 16'b????????????1000: begin
356 next_regs = {regs[15:4], 4'b0};
358 16'b???????????10000: begin
360 next_regs = {regs[15:5], 5'b0};
362 16'b??????????100000: begin
364 next_regs = {regs[15:6], 6'b0};
366 16'b?????????1000000: begin
368 next_regs = {regs[15:7], 7'b0};
370 16'b????????10000000: begin
372 next_regs = {regs[15:8], 8'b0};
374 16'b???????100000000: begin
376 next_regs = {regs[15:9], 9'b0};
378 16'b??????1000000000: begin
380 next_regs = {regs[15:10], 10'b0};
382 16'b?????10000000000: begin
384 next_regs = {regs[15:11], 11'b0};
386 16'b????100000000000: begin
388 next_regs = {regs[15:12], 12'b0};
390 16'b???1000000000000: begin
392 next_regs = {regs[15:13], 13'b0};
394 16'b??10000000000000: begin
396 next_regs = {regs[15:14], 14'b0};
398 16'b?100000000000000: begin
400 next_regs = {regs[15], 15'b0};
402 16'b1000000000000000: begin
411 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
412 if(cur_reg == 4'hF && insn[22]) begin
417 offset = prev_offset + 6'h4;
418 offset_sel = insn[24] ? offset : prev_offset;
419 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
421 next_write_reg = !rw_wait;
422 next_write_num = cur_reg;
423 next_write_data = rd_data;
427 cur_reg = prev_reg; /* whoops, do this one again */
431 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
434 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
438 if(next_regs == 16'b0) begin
439 next_lsm_state = 4'b0100;
445 next_write_reg = insn[21] /* writeback */;
446 next_write_num = insn[19:16];
447 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
448 next_lsm_state = 4'b1000;
449 $display("LDMSTM: Stage 3: Writing back");
453 next_lsm_state = 4'b0001;
457 if ((lsm_state == 4'b0001) && flush) begin /* Reject it. */
459 next_lsm_state = 4'b0001;
461 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
463 `DECODE_LDCSTC: if(!inbubble) begin
464 $display("WARNING: Unimplemented LDCSTC");
466 `DECODE_CDP: if(!inbubble) begin
473 /* XXX undefined instruction trap */
474 $display("WARNING: Possible CDP undefined instruction");
477 `DECODE_MRCMCR: if(!inbubble) begin
479 cp_rnw = insn[20] /* L */;
480 if (insn[20] == 0 /* store to coprocessor */)
483 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
484 next_write_reg = 1'b1;
485 next_write_num = insn[15:12];
486 next_write_data = cp_read;
488 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
497 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
499 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
504 if ((flush || delayedflush) && !outstall)
505 next_outbubble = 1'b1;