RegFile.v

   1 module RegFile(
   2         input clk,
   3         input [3:0] read_0,
   4         output reg [31:0] rdata_0,
   5         input [3:0] read_1,
   6         output reg [31:0] rdata_1,
   7         input [3:0] read_2,
   8         output reg [31:0] rdata_2,
   9         output reg [31:0] spsr,
  10         input [3:0] write,
  11         input write_req,
  12         input [31:0] write_data
  13         );
  14
  15         reg [31:0] regfile [0:15];
  16
  17         initial begin
  18                 regfile[4'h0] = 32'h00000005;
  19                 regfile[4'h1] = 32'h00000050;
  20                 regfile[4'h2] = 32'h00000500;
  21                 regfile[4'h3] = 32'h00005000;
  22                 regfile[4'h4] = 32'h00050000;
  23                 regfile[4'h5] = 32'h00500000;
  24                 regfile[4'h6] = 32'h05000000;
  25                 regfile[4'h7] = 32'h50000000;
  26                 regfile[4'h8] = 32'hA0000000;
  27                 regfile[4'h9] = 32'h0A000000;
  28                 regfile[4'hA] = 32'h00A00000;
  29                 regfile[4'hB] = 32'h000A0000;
  30                 regfile[4'hC] = 32'h0000A000;
  31                 regfile[4'hD] = 32'h00000A00;
  32                 regfile[4'hE] = 32'h000000A0;
  33                 regfile[4'hF] = 32'h00000000;   /* Start off claiming we are in user mode. */
  34         end
  35
  36         always @(*)
  37         begin
  38                 if ((read_0 == write) && write_req)
  39                         rdata_0 = write_data;
  40                 else
  41                         rdata_0 = regfile[read_0];
  42
  43                 if ((read_1 == write) && write_req)
  44                         rdata_1 = write_data;
  45                 else
  46                         rdata_1 = regfile[read_1];
  47
  48                 if ((read_2 == write) && write_req)
  49                         rdata_2 = write_data;
  50                 else
  51                         rdata_2 = regfile[read_2];
  52
  53                 spsr = regfile[4'hF];
  54         end
  55
  56         always @(posedge clk)
  57                 if (write_req)
  58                         regfile[write] <= write_data;
  59 endmodule