Fetch.v

   1 module Fetch(
   2         input clk,
   3         input Nrst,
   4
   5         output wire [31:0] rd_addr,
   6         output wire rd_req,
   7         input rd_wait,
   8         input [31:0] rd_data,
   9
  10         input stall,
  11         input jmp,
  12         input [31:0] jmppc,
  13         output reg bubble = 1,
  14         output reg [31:0] insn = 0,
  15         output reg [31:0] pc = 0);
  16
  17         reg [31:0] prevpc;
  18         reg [31:0] nextpc;
  19         initial
  20                 prevpc = 32'hFFFFFFFC;  /* ugh... the first pc we request will be this +4 */
  21         always @(negedge Nrst)
  22                 prevpc <= 32'hFFFFFFFC;
  23
  24         always @(*)
  25                 if (!Nrst)
  26                         nextpc = 32'hFFFFFFFC;
  27                 else if (stall) /* don't change any internal state */
  28                         nextpc = prevpc;
  29                 else if (jmp)
  30                         nextpc = jmppc;
  31                 else
  32                         nextpc = prevpc + 32'h4;
  33
  34         assign rd_addr = pc;
  35         assign rd_req = !stall;
  36
  37         always @(posedge clk)
  38         begin
  39                 if (!rd_wait || !Nrst)
  40                         prevpc <= nextpc;
  41                 if (!stall)
  42                 begin
  43                         bubble <= rd_wait;
  44                         insn <= rd_data;
  45                         pc <= nextpc;
  46                 end
  47         end
  48 endmodule