system.v

   1 `define BUS_ICACHE 1
   2 `define BUS_DCACHE 0
   3
   4 module System(input clk, input rst
   5 `ifdef verilator
   6 `else
   7         , output wire [8:0] sys_odata,
   8         input [8:0] sys_idata,
   9         output wire sys_tookdata
  10 `endif
  11         );
  12
  13         wire [7:0] bus_req;
  14         wire [7:0] bus_ack;
  15         wire [31:0] bus_addr;
  16         wire [31:0] bus_rdata;
  17         wire [31:0] bus_wdata;
  18         wire bus_rd, bus_wr;
  19         wire bus_ready;
  20
  21         wire bus_req_icache;
  22         wire bus_req_dcache;
  23         assign bus_req = {6'b0, bus_req_icache, bus_req_dcache};
  24         wire bus_ack_icache = bus_ack[`BUS_ICACHE];
  25         wire bus_ack_dcache = bus_ack[`BUS_DCACHE];
  26
  27         wire [31:0] bus_addr_icache;
  28         wire [31:0] bus_wdata_icache;
  29         wire bus_rd_icache;
  30         wire bus_wr_icache;
  31
  32         wire [31:0] bus_addr_dcache;
  33         wire [31:0] bus_wdata_dcache;
  34         wire bus_rd_dcache;
  35         wire bus_wr_dcache;
  36
  37         wire [31:0] bus_rdata_blockram;
  38         wire bus_ready_blockram;
  39
  40         assign bus_addr = bus_addr_icache | bus_addr_dcache;
  41         assign bus_rdata = bus_rdata_blockram;
  42         assign bus_wdata = bus_wdata_icache | bus_wdata_dcache;
  43         assign bus_rd = bus_rd_icache | bus_rd_dcache;
  44         assign bus_wr = bus_wr_icache | bus_wr_dcache;
  45         assign bus_ready = bus_ready_blockram;
  46
  47         wire [31:0] icache_rd_addr;
  48         wire icache_rd_req;
  49         wire icache_rd_wait;
  50         wire [31:0] icache_rd_data;
  51
  52         wire [31:0] dcache_addr;
  53         wire dcache_rd_req, dcache_wr_req;
  54         wire dcache_rw_wait;
  55         wire [31:0] dcache_wr_data, dcache_rd_data;
  56
  57         wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr, decode_out_cpsr;
  58         wire decode_out_carry;
  59
  60         wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2, regfile_read_3;
  61         wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_rdata_3, regfile_spsr;
  62         wire regfile_write;
  63         wire [3:0] regfile_write_reg;
  64         wire [31:0] regfile_write_data;
  65
  66         wire execute_out_write_reg;
  67         wire [3:0] execute_out_write_num;
  68         wire [31:0] execute_out_write_data;
  69         wire [31:0] execute_out_op0, execute_out_op1, execute_out_op2;
  70         wire [31:0] execute_out_cpsr, execute_out_spsr;
  71         wire execute_out_cpsrup;
  72
  73         wire jmp_out_execute, jmp_out_writeback;
  74         wire [31:0] jmppc_out_execute, jmppc_out_writeback;
  75         wire jmp = jmp_out_execute | jmp_out_writeback;
  76         wire [31:0] jmppc = jmppc_out_execute | jmppc_out_writeback;
  77
  78         wire memory_out_write_reg;
  79         wire [3:0] memory_out_write_num;
  80         wire [31:0] memory_out_write_data;
  81         wire [31:0] memory_out_cpsr, memory_out_spsr;
  82         wire memory_out_cpsrup;
  83
  84         wire [31:0] writeback_out_cpsr, writeback_out_spsr;
  85
  86         wire cp_ack_terminal;
  87         wire cp_busy_terminal;
  88         wire [31:0] cp_read_terminal;
  89
  90         wire cp_req;
  91         wire [31:0] cp_insn;
  92         wire cp_ack = cp_ack_terminal;
  93         wire cp_busy = cp_busy_terminal;
  94         wire cp_rnw;
  95         wire [31:0] cp_read = cp_read_terminal;
  96         wire [31:0] cp_write;
  97
  98         wire stall_cause_issue;
  99         wire stall_cause_execute;
 100         wire stall_cause_memory;
 101         wire bubble_out_fetch;
 102         wire bubble_out_issue;
 103         wire bubble_out_execute;
 104         wire bubble_out_memory;
 105         wire [31:0] insn_out_fetch;
 106         wire [31:0] insn_out_issue;
 107         wire [31:0] insn_out_execute;
 108         wire [31:0] insn_out_memory;
 109         wire [31:0] pc_out_fetch;
 110         wire [31:0] pc_out_issue;
 111         wire [31:0] pc_out_execute;
 112         wire [31:0] pc_out_memory;
 113
 114         wire Nrst = ~rst;
 115
 116         /*AUTOWIRE*/
 117         // Beginning of automatic wires (for undeclared instantiated-module outputs)
 118         wire            bubble_1a;              // From fetch of Fetch.v
 119         wire            bubble_2a;              // From issue of Issue.v
 120         wire            carry_2a;               // From decode of Decode.v
 121         wire [31:0]     cpsr_2a;                // From decode of Decode.v
 122         wire [31:0]     ic__rd_addr_0a;         // From fetch of Fetch.v
 123         wire [31:0]     ic__rd_data_1a;         // From icache of ICache.v
 124         wire            ic__rd_req_0a;          // From fetch of Fetch.v
 125         wire            ic__rd_wait_0a;         // From icache of ICache.v
 126         wire [31:0]     insn_1a;                // From fetch of Fetch.v
 127         wire [31:0]     insn_2a;                // From issue of Issue.v
 128         wire [31:0]     op0_2a;                 // From decode of Decode.v
 129         wire [31:0]     op1_2a;                 // From decode of Decode.v
 130         wire [31:0]     op2_2a;                 // From decode of Decode.v
 131         wire [31:0]     pc_1a;                  // From fetch of Fetch.v
 132         wire [31:0]     pc_2a;                  // From issue of Issue.v
 133         wire [31:0]     rf__rdata_0_1a;         // From regfile of RegFile.v
 134         wire [31:0]     rf__rdata_1_1a;         // From regfile of RegFile.v
 135         wire [31:0]     rf__rdata_2_1a;         // From regfile of RegFile.v
 136         wire [31:0]     rf__rdata_3_4a;         // From regfile of RegFile.v
 137         wire [3:0]      rf__read_0_1a;          // From decode of Decode.v
 138         wire [3:0]      rf__read_1_1a;          // From decode of Decode.v
 139         wire [3:0]      rf__read_2_1a;          // From decode of Decode.v
 140         wire [31:0]     spsr_2a;                // From decode of Decode.v
 141         wire            stall_0a;               // From issue of Issue.v
 142         // End of automatics
 143
 144         wire execute_out_backflush;
 145         wire writeback_out_backflush;
 146
 147         BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
 148
 149         /* XXX reset? */
 150         /* ICache AUTO_TEMPLATE (
 151                 .clk(clk),
 152                 .bus_req(bus_req_icache),
 153                 .bus_ack(bus_ack_icache),
 154                 .bus_addr(bus_addr_icache),
 155                 .bus_rdata(bus_rdata),
 156                 .bus_wdata(bus_wdata_icache),
 157                 .bus_rd(bus_rd_icache),
 158                 .bus_wr(bus_wr_icache),
 159                 .bus_ready(bus_ready),
 160                 ); */
 161         ICache icache(/*AUTOINST*/
 162                       // Outputs
 163                       .ic__rd_wait_0a   (ic__rd_wait_0a),
 164                       .ic__rd_data_1a   (ic__rd_data_1a[31:0]),
 165                       .bus_req          (bus_req_icache),        // Templated
 166                       .bus_addr         (bus_addr_icache),       // Templated
 167                       .bus_wdata        (bus_wdata_icache),      // Templated
 168                       .bus_rd           (bus_rd_icache),         // Templated
 169                       .bus_wr           (bus_wr_icache),         // Templated
 170                       // Inputs
 171                       .clk              (clk),                   // Templated
 172                       .ic__rd_addr_0a   (ic__rd_addr_0a[31:0]),
 173                       .ic__rd_req_0a    (ic__rd_req_0a),
 174                       .bus_ack          (bus_ack_icache),        // Templated
 175                       .bus_rdata        (bus_rdata),             // Templated
 176                       .bus_ready        (bus_ready));            // Templated
 177
 178         DCache dcache(
 179                 .clk(clk),
 180                 .addr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
 181                 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
 182                 .bus_req(bus_req_dcache), .bus_ack(bus_ack_dcache),
 183                 .bus_addr(bus_addr_dcache), .bus_rdata(bus_rdata),
 184                 .bus_wdata(bus_wdata_dcache), .bus_rd(bus_rd_dcache),
 185                 .bus_wr(bus_wr_dcache), .bus_ready(bus_ready));
 186
 187 `ifdef verilator
 188         BigBlockRAM
 189 `else
 190         BlockRAM
 191 `endif
 192         blockram(
 193                 .clk(clk),
 194                 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
 195                 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
 196                 .bus_ready(bus_ready_blockram));
 197
 198         /* Fetch AUTO_TEMPLATE (
 199                 .jmp_0a(jmp),
 200                 .jmppc_0a(jmppc),
 201                 );
 202         */
 203         Fetch fetch(
 204                 /*AUTOINST*/
 205                     // Outputs
 206                     .ic__rd_addr_0a     (ic__rd_addr_0a[31:0]),
 207                     .ic__rd_req_0a      (ic__rd_req_0a),
 208                     .bubble_1a          (bubble_1a),
 209                     .insn_1a            (insn_1a[31:0]),
 210                     .pc_1a              (pc_1a[31:0]),
 211                     // Inputs
 212                     .clk                (clk),
 213                     .Nrst               (Nrst),
 214                     .ic__rd_wait_0a     (ic__rd_wait_0a),
 215                     .ic__rd_data_1a     (ic__rd_data_1a[31:0]),
 216                     .stall_0a           (stall_0a),
 217                     .jmp_0a             (jmp),                   // Templated
 218                     .jmppc_0a           (jmppc));                // Templated
 219
 220         /* Issue AUTO_TEMPLATE (
 221                 .stall_1a(stall_cause_execute),
 222                 .flush_1a(execute_out_backflush | writeback_out_backflush),
 223                 .cpsr_1a(writeback_out_cpsr),
 224                 );
 225         */
 226         Issue issue(
 227                 /*AUTOINST*/
 228                     // Outputs
 229                     .stall_0a           (stall_0a),
 230                     .bubble_2a          (bubble_2a),
 231                     .pc_2a              (pc_2a[31:0]),
 232                     .insn_2a            (insn_2a[31:0]),
 233                     // Inputs
 234                     .clk                (clk),
 235                     .Nrst               (Nrst),
 236                     .stall_1a           (stall_cause_execute),   // Templated
 237                     .flush_1a           (execute_out_backflush | writeback_out_backflush), // Templated
 238                     .bubble_1a          (bubble_1a),
 239                     .insn_1a            (insn_1a[31:0]),
 240                     .pc_1a              (pc_1a[31:0]),
 241                     .cpsr_1a            (writeback_out_cpsr));   // Templated
 242
 243         /* RegFile AUTO_TEMPLATE (
 244                 .spsr(regfile_spsr),
 245                 .write(regfile_write),
 246                 .write_reg(regfile_write_reg),
 247                 .write_data(regfile_write_data),
 248                 );
 249         */
 250         wire [3:0] rf__read_3_4a;
 251         RegFile regfile(
 252                 /*AUTOINST*/
 253                         // Outputs
 254                         .rf__rdata_0_1a (rf__rdata_0_1a[31:0]),
 255                         .rf__rdata_1_1a (rf__rdata_1_1a[31:0]),
 256                         .rf__rdata_2_1a (rf__rdata_2_1a[31:0]),
 257                         .rf__rdata_3_4a (rf__rdata_3_4a[31:0]),
 258                         .spsr           (regfile_spsr),          // Templated
 259                         // Inputs
 260                         .clk            (clk),
 261                         .Nrst           (Nrst),
 262                         .rf__read_0_1a  (rf__read_0_1a[3:0]),
 263                         .rf__read_1_1a  (rf__read_1_1a[3:0]),
 264                         .rf__read_2_1a  (rf__read_2_1a[3:0]),
 265                         .rf__read_3_4a  (rf__read_3_4a[3:0]),
 266                         .write          (regfile_write),         // Templated
 267                         .write_reg      (regfile_write_reg),     // Templated
 268                         .write_data     (regfile_write_data));   // Templated
 269
 270         /* Decode AUTO_TEMPLATE (
 271                 .stall(stall_cause_execute),
 272                 .cpsr_1a(writeback_out_cpsr),
 273                 .spsr_1a(writeback_out_spsr),
 274                 );
 275         */
 276         Decode decode(
 277                 /*AUTOINST*/
 278                       // Outputs
 279                       .op0_2a           (op0_2a[31:0]),
 280                       .op1_2a           (op1_2a[31:0]),
 281                       .op2_2a           (op2_2a[31:0]),
 282                       .carry_2a         (carry_2a),
 283                       .cpsr_2a          (cpsr_2a[31:0]),
 284                       .spsr_2a          (spsr_2a[31:0]),
 285                       .rf__read_0_1a    (rf__read_0_1a[3:0]),
 286                       .rf__read_1_1a    (rf__read_1_1a[3:0]),
 287                       .rf__read_2_1a    (rf__read_2_1a[3:0]),
 288                       // Inputs
 289                       .clk              (clk),
 290                       .stall            (stall_cause_execute),   // Templated
 291                       .insn_1a          (insn_1a[31:0]),
 292                       .pc_1a            (pc_1a[31:0]),
 293                       .cpsr_1a          (writeback_out_cpsr),    // Templated
 294                       .spsr_1a          (writeback_out_spsr),    // Templated
 295                       .rf__rdata_0_1a   (rf__rdata_0_1a[31:0]),
 296                       .rf__rdata_1_1a   (rf__rdata_1_1a[31:0]),
 297                       .rf__rdata_2_1a   (rf__rdata_2_1a[31:0]));
 298
 299         /* Execute AUTO_TEMPLATE (
 300                 .stall_2a(stall_cause_memory),
 301                 .flush(writeback_out_backflush),
 302                 .outstall_2a(stall_cause_execute),
 303                 .bubble_3a(bubble_out_execute),
 304                 .write_reg_3a(execute_out_write_reg),
 305                 .write_num_3a(execute_out_write_num),
 306                 .write_data_3a(execute_out_write_data),
 307                 .jmp_2a(jmp_out_execute),
 308                 .jmppc_2a(jmppc_out_execute),
 309                 .pc_3a(pc_out_execute),
 310                 .insn_3a(insn_out_execute),
 311                 .op0_3a(execute_out_op0),
 312                 .op1_3a(execute_out_op1),
 313                 .op2_3a(execute_out_op2),
 314                 .outcpsr(execute_out_cpsr),
 315                 .outspsr(execute_out_spsr),
 316                 .outcpsrup(execute_out_cpsrup),
 317                 );
 318         */
 319         Execute execute(
 320                 /*AUTOINST*/
 321                         // Outputs
 322                         .outstall_2a    (stall_cause_execute),   // Templated
 323                         .bubble_3a      (bubble_out_execute),    // Templated
 324                         .outcpsr        (execute_out_cpsr),      // Templated
 325                         .outspsr        (execute_out_spsr),      // Templated
 326                         .outcpsrup      (execute_out_cpsrup),    // Templated
 327                         .write_reg_3a   (execute_out_write_reg), // Templated
 328                         .write_num_3a   (execute_out_write_num), // Templated
 329                         .write_data_3a  (execute_out_write_data), // Templated
 330                         .jmppc_2a       (jmppc_out_execute),     // Templated
 331                         .jmp_2a         (jmp_out_execute),       // Templated
 332                         .pc_3a          (pc_out_execute),        // Templated
 333                         .insn_3a        (insn_out_execute),      // Templated
 334                         .op0_3a         (execute_out_op0),       // Templated
 335                         .op1_3a         (execute_out_op1),       // Templated
 336                         .op2_3a         (execute_out_op2),       // Templated
 337                         // Inputs
 338                         .clk            (clk),
 339                         .Nrst           (Nrst),
 340                         .stall_2a       (stall_cause_memory),    // Templated
 341                         .flush          (writeback_out_backflush), // Templated
 342                         .bubble_2a      (bubble_2a),
 343                         .pc_2a          (pc_2a[31:0]),
 344                         .insn_2a        (insn_2a[31:0]),
 345                         .cpsr_2a        (cpsr_2a[31:0]),
 346                         .spsr_2a        (spsr_2a[31:0]),
 347                         .op0_2a         (op0_2a[31:0]),
 348                         .op1_2a         (op1_2a[31:0]),
 349                         .op2_2a         (op2_2a[31:0]),
 350                         .carry_2a       (carry_2a));
 351         assign execute_out_backflush = jmp;
 352
 353         assign cp_insn = insn_out_execute;
 354         Memory memory(
 355                 .clk(clk), .Nrst(~rst),
 356                 /* stall? */ .flush(writeback_out_backflush),
 357                 .busaddr(dcache_addr), .rd_req(dcache_rd_req), .wr_req(dcache_wr_req),
 358                 .rw_wait(dcache_rw_wait), .wr_data(dcache_wr_data), .rd_data(dcache_rd_data),
 359                 .st_read(rf__read_3_4a), .st_data(rf__rdata_3_4a),
 360                 .inbubble(bubble_out_execute), .pc(pc_out_execute), .insn(insn_out_execute),
 361                 .op0(execute_out_op0), .op1(execute_out_op1), .op2(execute_out_op2),
 362                 .spsr(execute_out_spsr), .cpsr(execute_out_cpsr), .cpsrup(execute_out_cpsrup),
 363                 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num), .write_data(execute_out_write_data),
 364                 .outstall(stall_cause_memory), .outbubble(bubble_out_memory),
 365                 .outpc(pc_out_memory), .outinsn(insn_out_memory),
 366                 .out_write_reg(memory_out_write_reg), .out_write_num(memory_out_write_num),
 367                 .out_write_data(memory_out_write_data),
 368                 .cp_req(cp_req), .cp_ack(cp_ack), .cp_busy(cp_busy), .cp_rnw(cp_rnw), .cp_read(cp_read), .cp_write(cp_write),
 369                 .outcpsr(memory_out_cpsr), .outspsr(memory_out_spsr), .outcpsrup(memory_out_cpsrup) /* XXX data_size */);
 370
 371         Terminal terminal(
 372                 .clk(clk),
 373                 .cp_req(cp_req), .cp_insn(cp_insn), .cp_ack(cp_ack_terminal), .cp_busy(cp_busy_terminal), .cp_rnw(cp_rnw),
 374                 .cp_read(cp_read_terminal), .cp_write(cp_write)
 375 `ifdef verilator
 376 `else
 377                 , .sys_odata(sys_odata), .sys_tookdata(sys_tookdata), .sys_idata(sys_idata)
 378 `endif
 379                 );
 380
 381         Writeback writeback(
 382                 .clk(clk),
 383                 .inbubble(bubble_out_memory),
 384                 .write_reg(memory_out_write_reg), .write_num(memory_out_write_num), .write_data(memory_out_write_data),
 385                 .cpsr(memory_out_cpsr), .spsr(memory_out_spsr), .cpsrup(memory_out_cpsrup),
 386                 .regfile_write(regfile_write), .regfile_write_reg(regfile_write_reg), .regfile_write_data(regfile_write_data),
 387                 .outcpsr(writeback_out_cpsr), .outspsr(writeback_out_spsr),
 388                 .jmp(jmp_out_writeback), .jmppc(jmppc_out_writeback));
 389         assign writeback_out_backflush = jmp_out_writeback;
 390
 391         reg [31:0] clockno = 0;
 392         always @(posedge clk)
 393         begin
 394                 clockno <= clockno + 1;
 395                 $display("------------------------------------------------------------------------------");
 396                 $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_1a, insn_1a, pc_1a);
 397                 $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_0a, bubble_2a, insn_2a, pc_2a);
 398                 $display("%3d: DECODE:                      op0 %08x, op1 %08x, op2 %08x, carry %d", clockno, op0_2a, op1_2a, op2_2a, carry_2a);
 399                 $display("%3d: EXEC:   Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d], Jmp: %d [%08x]", clockno, stall_cause_execute, bubble_out_execute, insn_out_execute, pc_out_execute, execute_out_write_reg, execute_out_write_data, execute_out_write_num, jmp_out_execute, jmppc_out_execute);
 400                 $display("%3d: MEMORY: Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x, Reg: %d, [%08x -> %d]", clockno, stall_cause_memory, bubble_out_memory, insn_out_memory, pc_out_memory, memory_out_write_reg, memory_out_write_data, memory_out_write_num);
 401                 $display("%3d: WRITEB:                      CPSR %08x, SPSR %08x, Reg: %d [%08x -> %d], Jmp: %d [%08x]", clockno, writeback_out_cpsr, writeback_out_spsr, regfile_write, regfile_write_data, regfile_write_reg, jmp_out_writeback, jmppc_out_writeback);
 402         end
 403 endmodule