Execute: Fix jumps while flush asserted. Set lr correctly in bl.
[firearm.git] / Decode.v
1 `include "ARM_Constants.v"
2
3 module Decode(
4         input clk,
5         input stall,
6         input [31:0] insn,
7         input [31:0] inpc,
8         input [31:0] incpsr,
9         input [31:0] inspsr,
10         output reg [31:0] op0,
11         output reg [31:0] op1,
12         output reg [31:0] op2,
13         output reg carry,
14         output reg [31:0] outcpsr,
15         output reg [31:0] outspsr,
16
17         output reg [3:0] read_0,
18         output reg [3:0] read_1,
19         output reg [3:0] read_2,
20         input [31:0] rdata_0,
21         input [31:0] rdata_1,
22         input [31:0] rdata_2
23         );
24
25         wire [31:0] regs0, regs1, regs2;
26         reg [31:0] rpc;
27         reg [31:0] op0_out, op1_out, op2_out;
28         reg carry_out;
29
30         /* shifter stuff */
31         wire [31:0] shift_oper;
32         wire [31:0] shift_res;
33         wire shift_cflag_out;
34         wire [31:0] rotate_res;
35
36         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
37         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
38         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
39
40         IREALLYHATEARMSHIFT shift(.insn(insn),
41                                   .operand(regs1),
42                                   .reg_amt(regs2),
43                                   .cflag_in(incpsr[`CPSR_C]),
44                                   .res(shift_res),
45                                   .cflag_out(shift_cflag_out));
46
47         SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
48                               .amt(insn[11:8]),
49                               .res(rotate_res));
50
51         always @(*)
52                 casez (insn)
53                 `DECODE_ALU_MULT,               /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
54 //              `DECODE_ALU_MUL_LONG,           /* Multiply long */
55                 `DECODE_ALU_MRS,                /* MRS (Transfer PSR to register) */
56                 `DECODE_ALU_MSR,                /* MSR (Transfer register to PSR) */
57                 `DECODE_ALU_MSR_FLAGS,          /* MSR (Transfer register or immediate to PSR, flag bits only) */
58                 `DECODE_ALU_SWP,                /* Atomic swap */
59                 `DECODE_ALU_BX,                 /* Branch and exchange */
60                 `DECODE_ALU_HDATA_REG,          /* Halfword transfer - register offset */
61                 `DECODE_ALU_HDATA_IMM,          /* Halfword transfer - register offset */
62                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
63                 `DECODE_LDRSTR,                 /* Single data transfer */
64                 `DECODE_LDMSTM,                 /* Block data transfer */
65                 `DECODE_BRANCH,                 /* Branch */
66                 `DECODE_LDCSTC,                 /* Coprocessor data transfer */
67                 `DECODE_CDP,                    /* Coprocessor data op */
68                 `DECODE_SWI:                    /* SWI */
69                         rpc = inpc + 8;
70                 `DECODE_MRCMCR:                 /* Coprocessor register transfer */
71                         rpc = inpc + 12;
72                 `DECODE_ALU:                    /* ALU */
73                         rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
74                 default:                        /* X everything else out */
75                         rpc = 32'hxxxxxxxx;
76                 endcase
77         
78         always @(*) begin
79                 read_0 = 4'hx;
80                 read_1 = 4'hx;
81                 read_2 = 4'hx;
82                 
83                 op0_out = 32'hxxxxxxxx;
84                 op1_out = 32'hxxxxxxxx;
85                 op2_out = 32'hxxxxxxxx;
86                 carry_out = 1'bx;
87                 
88                 casez (insn)
89                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
90                 begin
91                         read_0 = insn[15:12]; /* Rn */
92                         read_1 = insn[3:0];   /* Rm */
93                         read_2 = insn[11:8];  /* Rs */
94                         
95                         op0_out = regs0;
96                         op1_out = regs1;
97                         op2_out = regs2;
98                 end
99 //              `DECODE_ALU_MUL_LONG:   /* Multiply long */
100 //              begin
101 //                      read_0 = insn[11:8]; /* Rn */
102 //                      read_1 = insn[3:0];   /* Rm */
103 //                      read_2 = 4'b0;       /* anyus */
104 //
105 //                      op1_res = regs1;
106 //              end
107                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
108                 begin end
109                 `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */
110                 begin
111                         read_0 = insn[3:0];     /* Rm */
112                         
113                         op0_out = regs0;
114                 end
115                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
116                 begin
117                         read_0 = insn[3:0];     /* Rm */
118                         
119                         if(insn[25]) begin     /* the constant case */
120                                 op0_out = rotate_res;
121                         end else begin
122                                 op0_out = regs0;
123                         end
124                 end
125                 `DECODE_ALU_SWP:        /* Atomic swap */
126                 begin
127                         read_0 = insn[19:16]; /* Rn */
128                         read_1 = insn[3:0];   /* Rm */
129                         
130                         op0_out = regs0;
131                         op1_out = regs1;
132                 end
133                 `DECODE_ALU_BX:         /* Branch and exchange */
134                 begin
135                         read_0 = insn[3:0];   /* Rn */
136                         
137                         op0_out = regs0;
138                 end
139                 `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
140                 begin
141                         read_0 = insn[19:16];
142                         read_1 = insn[3:0];
143                         read_2 = insn[15:12];
144
145                         op0_out = regs0;
146                         op1_out = regs1;
147                         op2_out = regs2;
148                 end
149                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
150                 begin
151                         read_0 = insn[19:16];
152                         read_1 = insn[15:12];
153                         
154                         op0_out = regs0;
155                         op1_out = {24'b0, insn[11:8], insn[3:0]};
156                         op2_out = regs1;
157                 end
158                 `DECODE_ALU:            /* ALU */
159                 begin
160                         read_0 = insn[19:16]; /* Rn */
161                         read_1 = insn[3:0];   /* Rm */
162                         read_2 = insn[11:8];  /* Rs for shift */
163                         
164                         op0_out = regs0;
165                         if(insn[25]) begin     /* the constant case */
166                                 carry_out = incpsr[`CPSR_C];
167                                 op1_out = rotate_res;
168                         end else begin
169                                 carry_out = shift_cflag_out;
170                                 op1_out = shift_res;
171                         end
172                 end
173                 `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */
174                 begin
175                         /* eat shit */
176                 end
177                 `DECODE_LDRSTR:         /* Single data transfer */
178                 begin
179                         read_0 = insn[19:16]; /* Rn */
180                         read_1 = insn[3:0];   /* Rm */
181                         read_2 = insn[15:12];
182                         
183                         op0_out = regs0;
184                         if(insn[25]) begin
185                                 op1_out = {20'b0, insn[11:0]};
186                                 carry_out = incpsr[`CPSR_C];
187                         end else begin
188                                 op1_out = shift_res;
189                                 carry_out = shift_cflag_out;
190                         end
191                         op2_out = regs2;
192                 end
193                 `DECODE_LDMSTM:         /* Block data transfer */
194                 begin
195                         read_0 = insn[19:16];
196                         
197                         op0_out = regs0;
198                         op1_out = {16'b0, insn[15:0]};
199                 end
200                 `DECODE_BRANCH:         /* Branch */
201                 begin
202                         op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
203                 end
204                 `DECODE_LDCSTC:         /* Coprocessor data transfer */
205                 begin
206                         read_0 = insn[19:16];
207                         
208                         op0_out = regs0;
209                         op1_out = {24'b0, insn[7:0]};
210                 end
211                 `DECODE_CDP:            /* Coprocessor data op */
212                 begin
213                 end
214                 `DECODE_MRCMCR:         /* Coprocessor register transfer */
215                 begin
216                         read_0 = insn[15:12];
217                         
218                         op0_out = regs0;
219                 end
220                 `DECODE_SWI:            /* SWI */
221                 begin
222                 end
223                 default:
224                         $display("Undecoded instruction");
225                 endcase
226         end
227
228         
229         always @ (posedge clk) begin
230                 if (!stall)
231                 begin
232                         op0 <= op0_out;   /* Rn - always */
233                         op1 <= op1_out; /* 'operand 2' - Rm */
234                         op2 <= op2_out;   /* thirdedge - Rs */
235                         carry <= carry_out;
236                         outcpsr <= incpsr;
237                         outspsr <= inspsr;
238                 end
239         end
240
241 endmodule
242
243 module IREALLYHATEARMSHIFT(
244         input [31:0] insn,
245         input [31:0] operand,
246         input [31:0] reg_amt,
247         input cflag_in,
248         output reg [31:0] res,
249         output reg cflag_out
250 );
251         wire [5:0] shift_amt;
252         reg is_arith, is_rot;
253         wire rshift_cout;
254         wire [31:0] rshift_res;
255
256         assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
257                                    : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
258
259         SuckLessShifter barrel(.oper(operand),
260                                .carryin(cflag_in),
261                                .amt(shift_amt),
262                                .is_arith(is_arith),
263                                .is_rot(is_rot),
264                                .res(rshift_res),
265                                .carryout(rshift_cout));
266
267         always @(*)
268                 case (insn[6:5])
269                 `SHIFT_LSL: begin
270                         /* meaningless */
271                         is_rot = 1'b0;
272                         is_arith = 1'b0;
273                 end
274                 `SHIFT_LSR: begin
275                         is_rot = 1'b0;
276                         is_arith = 1'b0;
277                 end
278                 `SHIFT_ASR: begin
279                         is_rot = 1'b0;
280                         is_arith = 1'b1;
281                 end
282                 `SHIFT_ROR: begin
283                         is_rot = 1'b1;
284                         is_arith = 1'b0;
285                 end
286                 endcase
287
288         always @(*)
289                 case (insn[6:5]) /* shift type */
290                 `SHIFT_LSL:
291                         {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
292                 `SHIFT_LSR: begin
293                         res = rshift_res;
294                         cflag_out = rshift_cout;
295                 end
296                 `SHIFT_ASR: begin
297                         res = rshift_res;
298                         cflag_out = rshift_cout;
299                 end
300                 `SHIFT_ROR: begin
301                         if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
302                                 res = {cflag_in, operand[31:1]};
303                                 cflag_out = operand[0];
304                         end else begin
305                                 res = rshift_res;
306                                 cflag_out = rshift_cout;
307                         end
308                 end
309                 endcase
310 endmodule
311
312 module SuckLessShifter(
313         input [31:0] oper,
314         input carryin,
315         input [5:0] amt,
316         input is_arith,
317         input is_rot,
318         output wire [31:0] res,
319         output wire carryout
320 );
321
322         wire [32:0] stage1, stage2, stage3, stage4, stage5;
323
324         wire pushbits = is_arith & oper[31];
325
326         /* do a barrel shift */
327         assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
328         assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
329         assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
330         assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
331         assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
332         assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
333
334 endmodule
335
336 module SuckLessRotator(
337         input [31:0] oper,
338         input [3:0] amt,
339         output wire [31:0] res
340 );
341
342         wire [31:0] stage1, stage2, stage3;
343         assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
344         assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
345         assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
346         assign res    = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
347
348 endmodule
349
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