Add SPSR logic to Execute.
[firearm.git] / system.v
1 `define BUS_ICACHE 0
2
3 module System(input clk);
4         wire [7:0] bus_req;
5         wire [7:0] bus_ack;
6         wire [31:0] bus_addr;
7         wire [31:0] bus_rdata;
8         wire [31:0] bus_wdata;
9         wire bus_rd, bus_wr;
10         wire bus_ready;
11
12         wire bus_req_icache;    
13         assign bus_req = {7'b0, bus_req_icache};
14         wire bus_ack_icache = bus_ack[`BUS_ICACHE];
15         
16         wire [31:0] bus_addr_icache;
17         wire [31:0] bus_wdata_icache;
18         wire bus_rd_icache;
19         wire bus_wr_icache;
20         
21         wire [31:0] bus_rdata_blockram;
22         wire bus_ready_blockram;
23         
24         assign bus_addr = bus_addr_icache;
25         assign bus_rdata = bus_rdata_blockram;
26         assign bus_wdata = bus_wdata_icache;
27         assign bus_rd = bus_rd_icache;
28         assign bus_wr = bus_wr_icache;
29         assign bus_ready = bus_ready_blockram;
30         
31         wire [31:0] icache_rd_addr;
32         wire icache_rd_req;
33         wire icache_rd_wait;
34         wire [31:0] icache_rd_data;
35         
36         wire stall_cause_issue;
37         wire stall_cause_execute;
38         
39         wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2, decode_out_spsr;
40         wire decode_out_carry;
41         wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
42         wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2, regfile_spsr;
43         wire execute_out_stall, execute_out_bubble;
44         wire execute_out_write_reg;
45         wire [3:0] execute_out_write_num;
46         wire [31:0] execute_out_write_data;
47         
48         wire bubble_out_fetch;
49         wire bubble_out_issue;
50         wire [31:0] insn_out_fetch;
51         wire [31:0] insn_out_issue;
52         wire [31:0] pc_out_fetch;
53         wire [31:0] pc_out_issue;
54         
55         BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
56
57         ICache icache(
58                 .clk(clk),
59                 /* XXX reset? */
60                 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
61                 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
62                 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
63                 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
64                 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
65                 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
66         
67         BlockRAM blockram(
68                 .clk(clk),
69                 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
70                 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
71                 .bus_ready(bus_ready_blockram));
72
73         Fetch fetch(
74                 .clk(clk),
75                 .Nrst(1'b1 /* XXX */),
76                 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
77                 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
78                 .stall(stall_cause_issue), .jmp(1'b0 /* XXX */), .jmppc(32'b0 /* XXX */),
79                 .bubble(bubble_out_fetch), .insn(insn_out_fetch),
80                 .pc(pc_out_fetch));
81         
82         Issue issue(
83                 .clk(clk),
84                 .Nrst(1'b1 /* XXX */),
85                 .stall(stall_cause_execute), .flush(1'b0 /* XXX */),
86                 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
87                 .inpc(pc_out_fetch), .cpsr(32'b0 /* XXX */),
88                 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
89                 .outpc(pc_out_issue), .outinsn(insn_out_issue));
90         
91         RegFile regfile(
92                 .clk(clk),
93                 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
94                 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2),
95                 .spsr(regfile_spsr), .write(4'b0), .write_req(1'b0), .write_data(10 /* XXX */));
96         
97         Decode decode(
98                 .clk(clk),
99                 .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(32'b0 /* XXX */), .inspsr(regfile_spsr),
100                 .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
101                 .carry(decode_out_carry), .outspsr(decode_out_spsr),
102                 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
103                 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
104         
105         Execute execute(
106                 .clk(clk), .Nrst(1'b0),
107                 .stall(1'b0 /* XXX */), .flush(1'b0 /* XXX */),
108                 .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
109                 .cpsr(32'b0 /* XXX */), .spsr(decode_out_spsr), .op0(decode_out_op0), .op1(decode_out_op1),
110                 .op2(decode_out_op2), .carry(decode_out_carry),
111                 .outstall(stall_cause_execute), .outbubble(execute_out_bubble),
112                 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
113                 .write_data(execute_out_write_data));
114         
115         reg [31:0] clockno = 0;
116         always @(posedge clk)
117         begin
118                 clockno <= clockno + 1;
119                 $display("------------------------------------------------------------------------------");
120                 $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
121                 $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
122                 $display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
123                 $display("%3d: EXEC:   Stall: %d, Bubble: %d, Output: %d, [%08x -> %d]", clockno, stall_cause_execute, execute_out_bubble, execute_out_write_reg, execute_out_write_data, execute_out_write_num);
124         end
125 endmodule
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