1 `include "ARM_Constants.v"
8 output reg [31:0] busaddr,
12 output reg [31:0] wr_data,
15 /* regfile interface */
16 output reg [3:0] st_read,
27 input [3:0] write_num,
28 input [31:0] write_data,
33 output reg [31:0] outpc,
34 output reg [31:0] outinsn,
35 output reg out_write_reg = 1'b0,
36 output reg [3:0] out_write_num = 4'bxxxx,
37 output reg [31:0] out_write_data = 32'hxxxxxxxx
40 reg [31:0] addr, raddr;
41 reg next_notdone, next_inc_next;
42 reg [31:0] align_s1, align_s2, align_rddata;
46 wire [3:0] next_write_num;
47 wire [31:0] next_write_data;
49 reg [15:0] regs, next_regs;
58 outbubble <= next_outbubble;
59 out_write_reg <= next_write_reg;
60 out_write_num <= next_write_num;
61 out_write_data <= next_write_data;
62 notdone <= next_notdone;
63 inc_next <= next_inc_next;
73 wr_data = 32'hxxxxxxxx;
74 busaddr = 32'hxxxxxxxx;
77 next_write_reg = write_reg;
78 next_write_num = write_num;
79 next_write_data = write_data;
81 next_outbubble = inbubble;
85 `DECODE_LDRSTR_UNDEFINED: begin end
88 next_outbubble = rw_wait;
89 outstall = rw_wait | notdone;
91 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
92 raddr = insn[24] ? op0 : addr; /* pre/post increment */
93 busaddr = {raddr[31:2], 2'b0};
97 /* rotate to correct position */
98 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
99 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
100 /* select byte or word */
101 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
104 wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
106 else if(!inc_next) begin
107 next_write_reg = 1'b1;
108 next_write_num = insn[15:12];
109 next_write_data = align_rddata;
110 next_inc_next = 1'b1;
112 else if(insn[21]) begin
113 next_write_reg = 1'b1;
114 next_write_num = insn[19:16];
115 next_write_data = addr;
117 next_notdone = rw_wait & insn[20] & insn[21];
120 `DECODE_LDMSTM: begin
121 busaddr = {op0[31:2], 2'b0};
125 16'b???????????????1: begin
128 16'b??????????????10: begin
130 16'b?????????????100: begin
132 16'b????????????1000: begin
134 16'b???????????10000: begin
136 16'b??????????100000: begin
138 16'b?????????1000000: begin
140 16'b????????10000000: begin
142 16'b???????100000000: begin
144 16'b??????1000000000: begin
146 16'b?????10000000000: begin
148 16'b????100000000000: begin
150 16'b???1000000000000: begin
152 16'b??10000000000000: begin
154 16'b?100000000000000: begin
156 16'b1000000000000000: begin
159 next_inc_next = 1'b1;