Memory.v

   1 `include "ARM_Constants.v"
   2
   3 module Memory(
   4         input clk,
   5         input Nrst,
   6         input [31:0] pc,
   7         input [31:0] insn,
   8         input [31:0] base,
   9         input [31:0] offset,
  10
  11         /* bus interface */
  12         output reg [31:0] busaddr,
  13         output reg rd_req,
  14         output reg wr_req,
  15         input rw_wait,
  16         output reg [31:0] wr_data,
  17         input [31:0] rd_data,
  18
  19         /* regfile interface */
  20         output reg [3:0] st_read,
  21         input [31:0] st_data,
  22
  23         /* writeback to base */
  24         output reg writeback,
  25         output reg [3:0] regsel,
  26         output reg [31:0] regdata,
  27
  28         /* pc stuff */
  29         output reg [31:0] outpc,
  30         output reg [31:0] newpc,
  31
  32         /* stall */
  33         output outstall,
  34         output reg outbubble
  35 );
  36
  37         reg [31:0] addr, raddr, next_regdata, next_newpc;
  38         reg [3:0] next_regsel;
  39         reg next_writeback, next_notdone, next_inc_next;
  40         reg [31:0] align_s1, align_s2, align_rddata;
  41
  42         reg notdone = 1'b0;
  43         reg inc_next = 1'b0;
  44         assign outstall = rw_wait | notdone;
  45
  46         always @(*)
  47         begin
  48                 addr = 32'hxxxxxxxx;
  49                 raddr = 32'hxxxxxxxx;
  50                 rd_req = 1'b0;
  51                 wr_req = 1'b0;
  52                 wr_data = 32'hxxxxxxxx;
  53                 busaddr = 32'hxxxxxxxx;
  54                 outstall = 1'b0;
  55                 next_notdone = 1'b0;
  56                 next_regsel = 4'hx;
  57                 next_regdata = 32'hxxxxxxxx;
  58                 next_inc_next = 1'b0;
  59                 next_newpc = 32'hxxxxxxxx;
  60                 casez(insn)
  61                 `DECODE_LDRSTR_UNDEFINED: begin end
  62                 `DECODE_LDRSTR: begin
  63                         addr = insn[23] ? base + offset : base - offset; /* up/down select */
  64                         raddr = insn[24] ? base : addr;
  65                         busaddr = {raddr[31:2], 2'b0}; /* pre/post increment */
  66                         rd_req = insn[20];
  67                         wr_req = ~insn[20];
  68
  69                         align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
  70                         align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
  71                         align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
  72
  73                         if(!insn[20]) begin
  74                                 st_read = insn[15:12];
  75                                 wr_data = insn[22] ? {4{st_data[7:0]}} : st_data;
  76                         end
  77                         else if(!inc_next) begin /* store */
  78                                 next_writeback = 1'b1;
  79                                 next_regsel = insn[15:12];
  80                                 next_regdata = align_rddata;
  81                                 next_inc_next = 1'b1;
  82                         end
  83                         else if(insn[21]) begin
  84                                 next_writeback = 1'b1;
  85                                 next_regsel = insn[19:16];
  86                                 next_regdata = addr;
  87                         end
  88                         next_notdone = rw_wait & insn[20] & insn[21];
  89                 end
  90                 `DECODE_LDMSTM: begin
  91                 end
  92                 default: begin end
  93                 endcase
  94         end
  95
  96
  97         always @(posedge clk)
  98         begin
  99                 outpc <= pc;
 100                 outbubble <= rw_wait;
 101                 writeback <= next_writeback;
 102                 regsel <= next_regsel;
 103                 regdata <= next_regdata;
 104                 notdone <= next_notdone;
 105                 newpc <= next_newpc;
 106                 inc_next <= next_inc_next;
 107         end
 108
 109 endmodule