do some first pass Execute wiring
[firearm.git] / system.v
1 `define BUS_ICACHE 0
2
3 module System(input clk, output wire bubbleshield, output wire [31:0] insn, output wire [31:0] pc);
4         wire [7:0] bus_req;
5         wire [7:0] bus_ack;
6         wire [31:0] bus_addr;
7         wire [31:0] bus_rdata;
8         wire [31:0] bus_wdata;
9         wire bus_rd, bus_wr;
10         wire bus_ready;
11
12         wire bus_req_icache;    
13         assign bus_req = {7'b0, bus_req_icache};
14         wire bus_ack_icache = bus_ack[`BUS_ICACHE];
15         
16         wire [31:0] bus_addr_icache;
17         wire [31:0] bus_wdata_icache;
18         wire bus_rd_icache;
19         wire bus_wr_icache;
20         
21         wire [31:0] bus_rdata_blockram;
22         wire bus_ready_blockram;
23         
24         assign bus_addr = bus_addr_icache;
25         assign bus_rdata = bus_rdata_blockram;
26         assign bus_wdata = bus_wdata_icache;
27         assign bus_rd = bus_rd_icache;
28         assign bus_wr = bus_wr_icache;
29         assign bus_ready = bus_ready_blockram;
30         
31         wire [31:0] icache_rd_addr;
32         wire icache_rd_req;
33         wire icache_rd_wait;
34         wire [31:0] icache_rd_data;
35         
36         wire stall_cause_issue;
37         wire stall_cause_execute;
38         
39         wire [31:0] decode_out_op0, decode_out_op1, decode_out_op2;
40         wire decode_out_carry;
41         wire [3:0] regfile_read_0, regfile_read_1, regfile_read_2;
42         wire [31:0] regfile_rdata_0, regfile_rdata_1, regfile_rdata_2;
43         wire execute_out_stall, execute_out_bubble;
44         wire execute_out_write_reg;
45         wire [3:0] execute_out_write_num;
46         wire [31:0] execute_out_write_data;
47         
48         wire bubble_out_fetch;
49         wire bubble_out_issue;
50         wire [31:0] insn_out_fetch;
51         wire [31:0] insn_out_issue;
52         wire [31:0] pc_out_fetch;
53         wire [31:0] pc_out_issue;
54         
55         assign bubbleshield = bubble_out_issue;
56         assign insn = insn_out_issue;
57         assign pc = pc_out_issue;
58
59         BusArbiter busarbiter(.bus_req(bus_req), .bus_ack(bus_ack));
60
61         ICache icache(
62                 .clk(clk),
63                 /* XXX reset? */
64                 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
65                 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
66                 .bus_req(bus_req_icache), .bus_ack(bus_ack_icache),
67                 .bus_addr(bus_addr_icache), .bus_rdata(bus_rdata),
68                 .bus_wdata(bus_wdata_icache), .bus_rd(bus_rd_icache),
69                 .bus_wr(bus_wr_icache), .bus_ready(bus_ready));
70         
71         BlockRAM blockram(
72                 .clk(clk),
73                 .bus_addr(bus_addr), .bus_rdata(bus_rdata_blockram),
74                 .bus_wdata(bus_wdata), .bus_rd(bus_rd), .bus_wr(bus_wr),
75                 .bus_ready(bus_ready_blockram));
76
77         Fetch fetch(
78                 .clk(clk),
79                 .Nrst(1 /* XXX */),
80                 .rd_addr(icache_rd_addr), .rd_req(icache_rd_req),
81                 .rd_wait(icache_rd_wait), .rd_data(icache_rd_data),
82                 .stall(stall_cause_issue), .jmp(0 /* XXX */), .jmppc(0 /* XXX */),
83                 .bubble(bubble_out_fetch), .insn(insn_out_fetch),
84                 .pc(pc_out_fetch));
85         
86         Issue issue(
87                 .clk(clk),
88                 .Nrst(1 /* XXX */),
89                 .stall(stall_cause_execute), .flush(0 /* XXX */),
90                 .inbubble(bubble_out_fetch), .insn(insn_out_fetch),
91                 .inpc(pc_out_fetch), .cpsr(0 /* XXX */),
92                 .outstall(stall_cause_issue), .outbubble(bubble_out_issue),
93                 .outpc(pc_out_issue), .outinsn(insn_out_issue));
94         
95         RegFile regfile(
96                 .clk(clk),
97                 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2),
98                 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2),
99                 .write(0), .write_req(0), .write_data(0 /* XXX */));
100         
101         Decode decode(
102                 .clk(clk),
103                 .insn(insn_out_fetch), .inpc(pc_out_fetch), .incpsr(0 /* XXX */),
104                 .op0(decode_out_op0), .op1(decode_out_op1), .op2(decode_out_op2),
105                 .carry(decode_out_carry),
106                 .read_0(regfile_read_0), .read_1(regfile_read_1), .read_2(regfile_read_2), 
107                 .rdata_0(regfile_rdata_0), .rdata_1(regfile_rdata_1), .rdata_2(regfile_rdata_2));
108         
109         Execute execute(
110                 .clk(clk), .Nrst(0),
111                 .stall(0 /* XXX */), .flush(0 /* XXX */),
112                 .inbubble(bubble_out_issue), .pc(pc_out_issue), .insn(insn_out_issue),
113                 .cpsr(0 /* XXX */), .op0(decode_out_op0), .op1(decode_out_op1),
114                 .op2(decode_out_op2), .carry(decode_out_carry),
115                 .outstall(stall_cause_execute), .outbubble(execute_out_bubble),
116                 .write_reg(execute_out_write_reg), .write_num(execute_out_write_num),
117                 .write_data(execute_out_write_data));
118         
119         reg [31:0] clockno = 0;
120         always @(posedge clk)
121         begin
122                 clockno <= clockno + 1;
123                 $display("------------------------------------------------------------------------------");
124                 $display("%3d: FETCH:            Bubble: %d, Instruction: %08x, PC: %08x", clockno, bubble_out_fetch, insn_out_fetch, pc_out_fetch);
125                 $display("%3d: ISSUE:  Stall: %d, Bubble: %d, Instruction: %08x, PC: %08x", clockno, stall_cause_issue, bubble_out_issue, insn_out_issue, pc_out_issue);
126                 $display("%3d: DECODE:                      op1 %08x, op2 %08x, op3 %08x, carry %d", clockno, decode_out_op0, decode_out_op1, decode_out_op2, decode_out_carry);
127         end
128 endmodule
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