Fix up decode
[firearm.git] / Decode.v
1 `include "ARM_Constants.v"
2
3 module Decode(
4         input clk,
5         input [31:0] insn,
6         input [31:0] inpc,
7         input [31:0] incpsr,
8         output reg [31:0] op0,
9         output reg [31:0] op1,
10         output reg [31:0] op2,
11         output reg [31:0] outcpsr,
12
13         output [3:0] read_0,
14         output [3:0] read_1,
15         output [3:0] read_2,
16         input [31:0] rdata_0,
17         input [31:0] rdata_1,
18         input [31:0] rdata_2
19         );
20
21         wire [31:0] regs0, regs1, regs2, rpc;
22         wire [31:0] op1_res, cpsr;
23
24         /* shifter stuff */
25         wire [31:0] shift_oper;
26         wire [31:0] shift_res;
27         wire shift_cflag_out;
28
29         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
30         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
31         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
32
33         IHATEARMSHIFT blowme(.insn(insn),
34                              .operand(regs1),
35                              .reg_amt(regs2),
36                              .cflag_in(incpsr[`CPSR_C]),
37                              .res(shift_res),
38                              .cflag_out(shift_cflag_out));
39         
40         always @(*)
41                 casez (insn)
42                 32'b????000000??????????????1001????,   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
43 //              32'b????00001???????????????1001????,   /* Multiply long */
44                 32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
45                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
46                 32'b????00?10?1010001111????????????,   /* MSR (Transfer register or immediate to PSR, flag bits only) */
47                 32'b????00010?00????????00001001????,   /* Atomic swap */
48                 32'b????000100101111111111110001????,   /* Branch and exchange */
49                 32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
50                 32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
51                 32'b????011????????????????????1????,   /* Undefined. I hate ARM */
52                 32'b????01??????????????????????????,   /* Single data transfer */
53                 32'b????100?????????????????????????,   /* Block data transfer */
54                 32'b????101?????????????????????????,   /* Branch */
55                 32'b????110?????????????????????????,   /* Coprocessor data transfer */
56                 32'b????1110???????????????????0????,   /* Coprocessor data op */
57                 32'b????1110???????????????????1????,   /* Coprocessor register transfer */
58                 32'b????1111????????????????????????:   /* SWI */
59                         rpc = inpc - 8;
60                 32'b????00??????????????????????????:   /* ALU */
61                         rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
62                 default:                                /* X everything else out */
63                         rpc = 32'hxxxxxxxx;
64                 endcase
65
66         always @(*)
67                 casez (insn)
68                 32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
69                         read_0 = insn[15:12]; /* Rn */
70 //              32'b????00001???????????????1001????,   /* Multiply long */
71 //                      read_0 = insn[11:8]; /* Rn */
72                 32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
73                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
74                 32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
75                         read_0 = 4'hx;
76                 32'b????00??????????????????????????:   /* ALU */
77                         read_0 = insn[19:16]; /* Rn */
78                 32'b????00010?00????????00001001????:   /* Atomic swap */
79                         read_0 = insn[19:16]; /* Rn */
80                 32'b????000100101111111111110001????:   /* Branch and exchange */
81                         read_0 = insn[3:0];   /* Rn */
82                 32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
83                         read_0 = insn[19:16];
84                 32'b????000??1??????????00001??1????:   /* Halfword transfer - register offset */
85                         read_0 = insn[19:16];
86                 32'b????011????????????????????1????:   /* Undefined. I hate ARM */
87                         read_0 = 4'hx;
88                 32'b????01??????????????????????????:   /* Single data transfer */
89                         read_0 = insn[19:16]; /* Rn */
90                 32'b????100?????????????????????????:   /* Block data transfer */
91                         read_0 = insn[19:16];
92                 32'b????101?????????????????????????:   /* Branch */
93                         read_0 = 4'hx;
94                 32'b????110?????????????????????????:   /* Coprocessor data transfer */
95                         read_0 = insn[19:16];
96                 32'b????1110???????????????????0????,   /* Coprocessor data op */
97                 32'b????1110???????????????????1????,   /* Coprocessor register transfer */
98                 32'b????1111????????????????????????:   /* SWI */
99                         read_0 = 4'hx;
100                 default:
101                         read_0 = 4'hx;
102                 endcase
103         
104         always @(*)
105                 casez (insn)
106                 32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
107                         read_1 = insn[3:0];   /* Rm */
108 //              32'b????00001???????????????1001????:   /* Multiply long */
109 //                      read_1 = insn[3:0];   /* Rm */
110                 32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
111                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
112                 32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
113                         read_1 = 4'hx;
114                 32'b????00??????????????????????????:   /* ALU */
115                         read_1 = insn[3:0];   /* Rm */
116                 32'b????00010?00????????00001001????:   /* Atomic swap */
117                         read_1 = insn[3:0];   /* Rm */
118                 32'b????000100101111111111110001????:   /* Branch and exchange */
119                         read_1 = 4'hx;
120                 32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
121                         read_1 = insn[3:0];
122                 32'b????000??1??????????00001??1????:   /* Halfword transfer - register offset */
123                         read_1 = insn[3:0];
124                 32'b????011????????????????????1????:   /* Undefined. I hate ARM */
125                         read_1 = 4'hx;
126                 32'b????01??????????????????????????:   /* Single data transfer */
127                         read_1 = insn[3:0];   /* Rm */
128                 32'b????100?????????????????????????,   /* Block data transfer */
129                 32'b????101?????????????????????????,   /* Branch */
130                 32'b????110?????????????????????????,   /* Coprocessor data transfer */
131                 32'b????1110???????????????????0????,   /* Coprocessor data op */
132                 32'b????1110???????????????????1????,   /* Coprocessor register transfer */
133                 32'b????1111????????????????????????:   /* SWI */
134                         read_1 = 4'hx;
135                 default:
136                         read_1 = 4'hx;
137                 endcase
138         
139         always @(*)
140                 casez (insn)
141                 32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
142                         read_2 = insn[11:8];  /* Rs */
143 //              32'b????00001???????????????1001????:   /* Multiply long */
144 //                      read_2 = 4'b0;       /* anyus */
145                 32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
146                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
147                 32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
148                         read_2 = 4'hx;
149                 32'b????00??????????????????????????:   /* ALU */
150                         read_2 = insn[11:8];  /* Rs for shift */
151                 32'b????00010?00????????00001001????,   /* Atomic swap */
152                 32'b????000100101111111111110001????,   /* Branch and exchange */
153                 32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
154                 32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
155                 32'b????011????????????????????1????,   /* Undefined. I hate ARM */
156                 32'b????01??????????????????????????,   /* Single data transfer */
157                 32'b????100?????????????????????????,   /* Block data transfer */
158                 32'b????101?????????????????????????,   /* Branch */
159                 32'b????110?????????????????????????,   /* Coprocessor data transfer */
160                 32'b????1110???????????????????0????,   /* Coprocessor data op */
161                 32'b????1110???????????????????1????,   /* Coprocessor register transfer */
162                 32'b????1111????????????????????????:   /* SWI */
163                         read_2 = 4'hx;
164                 default:
165                         read_2 = 4'hx;
166                 endcase
167
168         always @ (*) begin
169                 op1_res = 32'hxxxxxxxx;
170                 cpsr = 32'hxxxxxxxx;
171                 casez (insn)
172                 32'b????000000??????????????1001????: begin /* Multiply */
173                         op1_res = regs1;
174                         cpsr = incpsr;
175                 end
176 //              32'b????00001???????????????1001????: begin /* Multiply long */
177 //                      op1_res = regs1;
178 //              end
179                 32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
180                         cpsr = incpsr;
181                 end
182                 32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
183                         cpsr = incpsr;
184                 end
185                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits onry) */
186                         cpsr = incpsr;
187                 end
188                 32'b????00??????????????????????????: begin /* ALU */
189                         if(insn[25]) begin     /* the constant case */
190                                 cpsr = incpsr;
191                                 op1_res = ({24'b0, insn[7:0]} >> {insn[11:8], 1'b0}) | ({24'b0, insn[7:0]} << (5'b0 - {insn[11:8], 1'b0}));
192                         end else begin
193                                 cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
194                                 op1_res = shift_res;
195                         end
196                 end
197                 32'b????00010?00????????00001001????: begin /* Atomic swap */
198                         op1_res = regs1;
199                 end
200                 32'b????000100101111111111110001????: begin /* Branch and exchange */
201                         cpsr = incpsr;
202                 end
203                 32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
204                         op1_res = regs1;
205                         cpsr = incpsr;
206                 end
207                 32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
208                         op1_res = {24'b0, insn[11:8], insn[3:0]};
209                         cpsr = incpsr;
210                 end
211                 32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
212                         /* eat shit */
213                 end
214                 32'b????01??????????????????????????: begin /* Single data transfer */
215                         if(insn[25]) begin
216                                 op1_res = {20'b0, insn[11:0]};
217                                 cpsr = incpsr;
218                         end else begin
219                                 op1_res = shift_res;
220                                 cpsr = {incpsr[31:30], shift_cflag_out, incpsr[28:0]};
221                         end
222                 end
223                 32'b????100?????????????????????????: begin /* Block data transfer */
224                         op1_res = {16'b0, insn[15:0]};
225                         cpsr = incpsr;
226                 end
227                 32'b????101?????????????????????????: begin /* Branch */
228                         op1_res = {{6{insn[23]}}, insn[23:0], 2'b0};
229                         cpsr = incpsr;
230                 end
231                 32'b????110?????????????????????????: begin /* Coprocessor data transfer */
232                         op1_res = {24'b0, insn[7:0]};
233                         cpsr = incpsr;
234                 end
235                 32'b????1110???????????????????0????: begin /* Coprocessor data op */
236                         cpsr = incpsr;
237                 end
238                 32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
239                         cpsr = incpsr;
240                 end
241                 32'b????1111????????????????????????: begin /* SWI */
242                         cpsr = incpsr;
243                 end
244                 default: begin end
245                 endcase
246         end
247
248         always @ (posedge clk) begin
249                 op0 <= regs0;   /* Rn - always */
250                 op1 <= op1_res; /* 'operand 2' - Rm */
251                 op2 <= regs2;   /* thirdedge - Rs */
252                 outcpsr <= cpsr;
253         end
254
255 endmodule
256
257 module IHATEARMSHIFT(
258         input [31:0] insn,
259         input [31:0] operand,
260         input [31:0] reg_amt,
261         input cflag_in,
262         output [31:0] res,
263         output cflag_out
264 );
265         wire [5:0] shift_amt;
266         wire elanus;
267
268
269         /* might want to write our own damn shifter that does arithmetic/logical efficiently and stuff */
270         always @(*)
271                 if(insn[4]) begin
272                         shift_amt = {|reg_amt[7:5], reg_amt[4:0]};
273                         elanus = 1'b1;
274                 end else begin
275                         shift_amt = {insn[11:7] == 5'b0, insn[11:7]};
276                         elanus = 1'b0;
277                 end
278         
279         always @(*)
280                 case (insn[6:5]) /* shift type */
281                 `SHIFT_LSL: begin
282                         {cflag_out, res} = {cflag_in, operand} << {elanus & shift_amt[5], shift_amt[4:0]};
283                 end
284                 `SHIFT_LSR: begin
285                         {res, cflag_out} = {operand, cflag_in} >> shift_amt;
286                 end
287                 `SHIFT_ASR: begin
288                         {res, cflag_out} = {operand, cflag_in} >> shift_amt | (operand[31] ? ~(33'h1FFFFFFFF >> shift_amt) : 33'b0);
289                 end
290                 `SHIFT_ROR: begin
291                         if(!elanus && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
292                                 res = {cflag_in, operand[31:1]};
293                                 cflag_out = operand[0];
294                         end else if(shift_amt == 6'b0) begin
295                                 res = operand;
296                                 cflag_out = cflag_in;
297                         end else begin
298                                 res = operand >> shift_amt[4:0] | operand << (5'b0 - shift_amt[4:0]);
299                                 cflag_out = operand[shift_amt[4:0] - 5'b1];
300                         end
301                 end
302                 endcase
303 endmodule
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