Memory: Input renaming pass.
[firearm.git] / Memory.v
1 `include "ARM_Constants.v"
2
3 `define SWP_READING     2'b01
4 `define SWP_WRITING     2'b10
5
6 `define LSRH_MEMIO      3'b001
7 `define LSRH_BASEWB     3'b010
8 `define LSRH_WBFLUSH    3'b100
9
10 `define LSR_MEMIO       4'b0001
11 `define LSR_STRB_WR     4'b0010
12 `define LSR_BASEWB      4'b0100
13 `define LSR_WBFLUSH     4'b1000
14
15 `define LSM_SETUP       4'b0001
16 `define LSM_MEMIO       4'b0010
17 `define LSM_BASEWB      4'b0100
18 `define LSM_WBFLUSH     4'b1000
19
20
21 module Memory(
22         input clk,
23         input Nrst,
24
25         input flush,
26
27         /* bus interface */
28         output reg [31:0] dc__addr_3a,
29         output reg dc__rd_req_3a,
30         output reg dc__wr_req_3a,
31         input dc__rw_wait_3a,
32         output reg [31:0] dc__wr_data_3a,
33         input [31:0] dc__rd_data_3a,
34         output reg [2:0] dc__data_size_3a,
35
36         /* regfile interface */
37         output reg [3:0] rf__read_3_3a,
38         input [31:0] rf__rdata_3_3a,
39         
40         /* Coprocessor interface */
41         output reg cp_req,
42         input cp_ack,
43         input cp_busy,
44         output reg cp_rnw,      /* 1 = read from CP, 0 = write to CP */
45         input [31:0] cp_read,
46         output reg [31:0] cp_write,
47         
48         /* stage inputs */
49         input bubble_3a,
50         input [31:0] pc_3a,
51         input [31:0] insn_3a,
52         input [31:0] op0_3a,
53         input [31:0] op1_3a,
54         input [31:0] op2_3a,
55         input [31:0] spsr_3a,
56         input [31:0] cpsr_3a,
57         input cpsrup_3a,
58         input write_reg_3a,
59         input [3:0] write_num_3a,
60         input [31:0] write_data_3a,
61
62         /* outputs */
63         output reg outstall,
64         output reg outbubble,
65         output reg [31:0] outpc,
66         output reg [31:0] outinsn,
67         output reg out_write_reg = 1'b0,
68         output reg [3:0] out_write_num = 4'bxxxx,
69         output reg [31:0] out_write_data = 32'hxxxxxxxx,
70         output reg [31:0] outspsr = 32'hxxxxxxxx,
71         output reg [31:0] outcpsr = 32'hxxxxxxxx,
72         output reg outcpsrup = 1'hx
73         );
74
75         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
76         reg next_outcpsrup;
77         reg [31:0] prevaddr;
78         reg [3:0] next_regsel, cur_reg, prev_reg;
79         reg next_writeback;
80
81         reg next_outbubble;     
82         reg next_write_reg;
83         reg [3:0] next_write_num;
84         reg [31:0] next_write_data;
85
86         reg [3:0] lsr_state = 4'b0001, next_lsr_state;
87         reg [31:0] align_s1, align_s2, align_rddata;
88
89         reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
90         reg [31:0] lsrh_rddata;
91         reg [15:0] lsrh_rddata_s1;
92         reg [7:0] lsrh_rddata_s2;
93
94         reg [15:0] regs, next_regs;
95         reg [3:0] lsm_state = 4'b0001, next_lsm_state;
96         reg [5:0] offset, prev_offset, offset_sel;
97
98         reg [31:0] swp_oldval, next_swp_oldval;
99         reg [1:0] swp_state = 2'b01, next_swp_state;
100         
101         reg do_rd_data_latch;
102         reg [31:0] rd_data_latch = 32'hxxxxxxxx;
103
104         always @(posedge clk)
105         begin
106                 outpc <= pc_3a;
107                 outinsn <= insn_3a;
108                 outbubble <= next_outbubble;
109                 out_write_reg <= next_write_reg;
110                 out_write_num <= next_write_num;
111                 out_write_data <= next_write_data;
112                 if (!dc__rw_wait_3a)
113                         prev_offset <= offset;
114                 prev_raddr <= raddr;
115                 outcpsr <= next_outcpsr;
116                 outspsr <= spsr_3a;
117                 outcpsrup <= next_outcpsrup;
118                 swp_state <= next_swp_state;
119                 lsm_state <= next_lsm_state;
120                 lsr_state <= next_lsr_state;
121                 lsrh_state <= next_lsrh_state;
122                 if (do_rd_data_latch)
123                         rd_data_latch <= dc__rd_data_3a;
124                 swp_oldval <= next_swp_oldval;
125                 prevaddr <= addr;
126         end
127         
128         reg delayedflush = 0;
129         always @(posedge clk)
130                 if (flush && outstall /* halp! I can't do it now, maybe later? */)
131                         delayedflush <= 1;
132                 else if (!outstall /* anything has been handled this time around */)
133                         delayedflush <= 0;
134         
135         /* Drive the state machines and stall. */
136         always @(*)
137         begin
138                 outstall = 1'b0;
139                 next_lsm_state = lsm_state;
140                 next_lsr_state = lsr_state;
141                 next_lsrh_state = lsrh_state;
142                 next_swp_state = swp_state;
143                 casez(insn_3a)
144                 `DECODE_ALU_SWP: if(!bubble_3a) begin
145                         case(swp_state)
146                         `SWP_READING: begin
147                                 outstall = 1'b1;
148                                 if (!dc__rw_wait_3a)
149                                         next_swp_state = `SWP_WRITING;
150                                 $display("SWP: read stage");
151                         end
152                         `SWP_WRITING: begin
153                                 outstall = dc__rw_wait_3a;
154                                 if(!dc__rw_wait_3a)
155                                         next_swp_state = `SWP_READING;
156                                 $display("SWP: write stage");
157                         end
158                         default: begin
159                                 outstall = 1'bx;
160                                 next_swp_state = 2'bxx;
161                         end
162                         endcase
163                 end
164                 `DECODE_ALU_MULT: begin
165                         outstall = 1'b0;        /* XXX work around for Xilinx bug */
166                         next_lsrh_state = lsrh_state;
167                 end
168                 `DECODE_ALU_HDATA_REG,
169                 `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
170                         case(lsrh_state)
171                         `LSRH_MEMIO: begin
172                                 outstall = dc__rw_wait_3a;
173                                 if(insn_3a[21] | !insn_3a[24]) begin
174                                         outstall = 1'b1;
175                                         if(!dc__rw_wait_3a)
176                                                 next_lsrh_state = `LSRH_BASEWB;
177                                 end
178                                 
179                                 if (flush) /* special case! */ begin
180                                         outstall = 1'b0;
181                                         next_lsrh_state = `LSRH_MEMIO;
182                                 end
183                                 
184                                 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", dc__rd_req_3a, dc__wr_req_3a);
185                         end
186                         `LSRH_BASEWB: begin
187                                 outstall = 1'b1;
188                                 next_lsrh_state = `LSRH_WBFLUSH;
189                         end
190                         `LSRH_WBFLUSH: begin
191                                 outstall = 1'b0;
192                                 next_lsrh_state = `LSRH_MEMIO;
193                         end
194                         default: begin
195                                 outstall = 1'bx;
196                                 next_lsrh_state = 3'bxxx;
197                         end
198                         endcase
199                 end
200                 `DECODE_LDRSTR_UNDEFINED: begin end
201                 `DECODE_LDRSTR: if(!bubble_3a) begin
202                         outstall = dc__rw_wait_3a;
203                         case(lsr_state)
204                         `LSR_MEMIO: begin
205                                 outstall = dc__rw_wait_3a;
206                                 next_lsr_state = `LSR_MEMIO;
207                                 if (insn_3a[22] /* B */ && !insn_3a[20] /* L */) begin  /* i.e., strb */
208                                         outstall = 1'b1;
209                                         if (!dc__rw_wait_3a)
210                                                 next_lsr_state = `LSR_STRB_WR;
211                                 end else if (insn_3a[21] /* W */ || !insn_3a[24] /* P */) begin /* writeback needed */
212                                         outstall = 1'b1;
213                                         if (!dc__rw_wait_3a)
214                                                 next_lsr_state = `LSR_BASEWB;
215                                 end
216                                 
217                                 if (flush) begin
218                                         outstall = 1'b0;
219                                         next_lsr_state = `LSR_MEMIO;
220                                 end
221                                 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", dc__rd_req_3a, dc__wr_req_3a, raddr, dc__rw_wait_3a);
222                         end
223                         `LSR_STRB_WR: begin
224                                 outstall = 1;
225                                 if(insn_3a[21] /* W */ | !insn_3a[24] /* P */) begin
226                                         if(!dc__rw_wait_3a)
227                                                 next_lsr_state = `LSR_BASEWB;
228                                 end else if (!dc__rw_wait_3a)
229                                         next_lsr_state = `LSR_WBFLUSH;
230                                 $display("LDRSTR: Handling STRB");
231                         end
232                         `LSR_BASEWB: begin
233                                 outstall = 1;
234                                 next_lsr_state = `LSR_WBFLUSH;
235                         end
236                         `LSR_WBFLUSH: begin
237                                 outstall = 0;
238                                 next_lsr_state = `LSR_MEMIO;
239                         end
240                         default: begin
241                                 outstall = 1'bx;
242                                 next_lsr_state = 4'bxxxx;
243                         end
244                         endcase
245                         $display("LDRSTR: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", bubble_3a, insn_3a, lsr_state, next_lsr_state, outstall);
246                 end
247                 `DECODE_LDMSTM: if(!bubble_3a) begin
248                         outstall = dc__rw_wait_3a;
249                         case(lsm_state)
250                         `LSM_SETUP: begin
251                                 outstall = 1'b1;
252                                 next_lsm_state = `LSM_MEMIO;
253                                 if (flush) begin
254                                         outstall = 1'b0;
255                                         next_lsm_state = `LSM_SETUP;
256                                 end
257                                 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0_3a, op1_3a[15:0]);
258                         end
259                         `LSM_MEMIO: begin
260                                 outstall = 1'b1;
261                                 if(next_regs == 16'b0 && !dc__rw_wait_3a) begin
262                                         next_lsm_state = `LSM_BASEWB;
263                                 end
264                                 
265                                 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, rf__rdata_3_3a, dc__addr_3a);
266                         end
267                         `LSM_BASEWB: begin
268                                 outstall = 1;
269                                 next_lsm_state = `LSM_WBFLUSH;
270                                 $display("LDMSTM: Stage 3: Writing back");
271                         end
272                         `LSM_WBFLUSH: begin
273                                 outstall = 0;
274                                 next_lsm_state = `LSM_SETUP;
275                         end
276                         default: begin
277                                 outstall = 1'bx;
278                                 next_lsm_state = 4'bxxxx;
279                         end
280                         endcase
281                         $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", bubble_3a, insn_3a, lsm_state, next_lsm_state, outstall);
282                 end
283                 `DECODE_LDCSTC: if(!bubble_3a) begin
284                         $display("WARNING: Unimplemented LDCSTC");
285                 end
286                 `DECODE_CDP: if (!bubble_3a) begin
287                         if (cp_busy) begin
288                                 outstall = 1;
289                         end
290                         if (!cp_ack) begin
291                                 /* XXX undefined instruction trap */
292                                 $display("WARNING: Possible CDP undefined instruction");
293                         end
294                 end
295                 `DECODE_MRCMCR: if (!bubble_3a) begin
296                         if (cp_busy) begin
297                                 outstall = 1;
298                         end
299                         if (!cp_ack) begin
300                                 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
301                         end
302                         $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
303                 end
304                 default: begin end
305                 endcase
306         end
307         
308         /* Coprocessor input. */
309         always @(*)
310         begin
311                 cp_req = 0;
312                 cp_rnw = 1'bx;
313                 cp_write = 32'hxxxxxxxx;
314                 casez (insn_3a)
315                 `DECODE_CDP: if(!bubble_3a) begin
316                         cp_req = 1;
317                 end
318                 `DECODE_MRCMCR: if(!bubble_3a) begin
319                         cp_req = 1;
320                         cp_rnw = insn_3a[20] /* L */;
321                         if (insn_3a[20] == 0 /* store to coprocessor */)
322                                 cp_write = op0_3a;
323                 end
324                 endcase
325         end
326         
327         /* Register output logic. */
328         always @(*)
329         begin
330                 next_write_reg = write_reg_3a;
331                 next_write_num = write_num_3a;
332                 next_write_data = write_data_3a;
333                 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr_3a;
334                 next_outcpsrup = cpsrup_3a;
335                 
336                 casez(insn_3a)
337                 `DECODE_ALU_SWP: if (!bubble_3a) begin
338                         next_write_reg = 1'bx;
339                         next_write_num = 4'bxxxx;
340                         next_write_data = 32'hxxxxxxxx;
341                         case(swp_state)
342                         `SWP_READING:
343                                 next_write_reg = 1'b0;
344                         `SWP_WRITING: begin
345                                 next_write_reg = 1'b1;
346                                 next_write_num = insn_3a[15:12];
347                                 next_write_data = insn_3a[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
348                         end
349                         default: begin end
350                         endcase
351                 end
352                 `DECODE_ALU_MULT: begin
353                         next_write_reg = write_reg_3a;  /* XXX workaround for ISE 10.1 bug */
354                         next_write_num = write_num_3a;
355                         next_write_data = write_data_3a;
356                         next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr_3a;
357                         next_outcpsrup = cpsrup_3a;
358                 end
359                 `DECODE_ALU_HDATA_REG,
360                 `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
361                         next_write_reg = 1'bx;
362                         next_write_num = 4'bxxxx;
363                         next_write_data = 32'hxxxxxxxx;
364                         case(lsrh_state)
365                         `LSRH_MEMIO: begin
366                                 next_write_num = insn_3a[15:12];
367                                 next_write_data = lsrh_rddata;
368                                 if(insn_3a[20]) begin
369                                         next_write_reg = 1'b1;
370                                 end
371                         end
372                         `LSRH_BASEWB: begin
373                                 next_write_reg = 1'b1;
374                                 next_write_num = insn_3a[19:16];
375                                 next_write_data = addr;
376                         end
377                         `LSRH_WBFLUSH:
378                                 next_write_reg = 1'b0;
379                         default: begin end
380                         endcase
381                 end
382                 `DECODE_LDRSTR_UNDEFINED: begin end
383                 `DECODE_LDRSTR: if(!bubble_3a) begin
384                         next_write_reg = 1'bx;
385                         next_write_num = 4'bxxxx;
386                         next_write_data = 32'hxxxxxxxx;
387                         case(lsr_state)
388                         `LSR_MEMIO: begin
389                                 next_write_reg = insn_3a[20] /* L */;
390                                 next_write_num = insn_3a[15:12];
391                                 if(insn_3a[20] /* L */) begin
392                                         next_write_data = insn_3a[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
393                                 end
394                         end
395                         `LSR_STRB_WR:
396                                 next_write_reg = 1'b0;
397                         `LSR_BASEWB: begin
398                                 next_write_reg = 1'b1;
399                                 next_write_num = insn_3a[19:16];
400                                 next_write_data = addr;
401                         end
402                         `LSR_WBFLUSH:
403                                 next_write_reg = 1'b0;
404                         default: begin end
405                         endcase
406                 end
407                 `DECODE_LDMSTM: if(!bubble_3a) begin
408                         next_write_reg = 1'bx;
409                         next_write_num = 4'bxxxx;
410                         next_write_data = 32'hxxxxxxxx;
411                         case(lsm_state)
412                         `LSM_SETUP:
413                                 next_write_reg = 1'b0;
414                         `LSM_MEMIO: begin
415                                 if(insn_3a[20] /* L */) begin
416                                         next_write_reg = !dc__rw_wait_3a;
417                                         next_write_num = cur_reg;
418                                         next_write_data = dc__rd_data_3a;
419                                 end else
420                                         next_write_reg = 1'b0;
421                         end
422                         `LSM_BASEWB: begin
423                                 next_write_reg = insn_3a[21] /* writeback */;
424                                 next_write_num = insn_3a[19:16];
425                                 next_write_data = insn_3a[23] ? op0_3a + {26'b0, prev_offset} : op0_3a - {26'b0, prev_offset};
426                                 if(cur_reg == 4'hF && insn_3a[22]) begin
427                                         next_outcpsr = spsr_3a;
428                                         next_outcpsrup = 1;
429                                 end
430                         end
431                         `LSM_WBFLUSH:
432                                 next_write_reg = 1'b0;
433                         default: begin end
434                         endcase
435                 end
436                 `DECODE_MRCMCR: if(!bubble_3a) begin
437                         next_write_reg = 1'bx;
438                         next_write_num = 4'bxxxx;
439                         next_write_data = 32'hxxxxxxxx;
440                         next_outcpsr = 32'hxxxxxxxx;
441                         next_outcpsrup = 1'bx;
442                         if (insn_3a[20] == 1 /* load from coprocessor */)
443                                 if (insn_3a[15:12] != 4'hF /* Fuck you ARM */) begin
444                                         next_write_reg = 1'b1;
445                                         next_write_num = insn_3a[15:12];
446                                         next_write_data = cp_read;
447                                 end else begin
448                                         next_outcpsr = {cp_read[31:28], cpsr_3a[27:0]};
449                                         next_outcpsrup = 1;
450                                 end
451                 end
452                 endcase
453         end
454         
455         /* Bus/address control logic. */
456         always @(*)
457         begin
458                 dc__rd_req_3a = 1'b0;
459                 dc__wr_req_3a = 1'b0;
460                 offset = prev_offset;
461                 addr = prevaddr;
462                 raddr = 32'hxxxxxxxx;
463                 dc__addr_3a = 32'hxxxxxxxx;
464                 dc__data_size_3a = 3'bxxx;
465                 
466                 casez(insn_3a)
467                 `DECODE_ALU_SWP: if(!bubble_3a) begin
468                         dc__addr_3a = {op0_3a[31:2], 2'b0};
469                         dc__data_size_3a = insn_3a[22] ? 3'b001 : 3'b100;
470                         case(swp_state)
471                         `SWP_READING:
472                                 dc__rd_req_3a = 1'b1;
473                         `SWP_WRITING:
474                                 dc__wr_req_3a = 1'b1;
475                         default: begin end
476                         endcase
477                 end
478                 `DECODE_ALU_MULT: begin
479                         dc__rd_req_3a = 1'b0;   /* XXX workaround for Xilinx bug */
480                         dc__wr_req_3a = 1'b0;
481                         offset = prev_offset;
482                         addr = prevaddr;
483                 end
484                 `DECODE_ALU_HDATA_REG,
485                 `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
486                         addr = insn_3a[23] ? op0_3a + op1_3a : op0_3a - op1_3a; /* up/down select */
487                         raddr = insn_3a[24] ? op0_3a : addr; /* pre/post increment */
488                         dc__addr_3a = raddr;
489                         /* rotate to correct position */
490                         case(insn_3a[6:5])
491                         2'b01: /* unsigned half */
492                                 dc__data_size_3a = 3'b010;
493                         2'b10: /* signed byte */
494                                 dc__data_size_3a = 3'b001;
495                         2'b11: /* signed half */
496                                 dc__data_size_3a = 3'b010;
497                         default: begin
498                                 dc__data_size_3a = 3'bxxx;
499                         end
500                         endcase
501                         
502                         case(lsrh_state)
503                         `LSRH_MEMIO: begin
504                                 dc__rd_req_3a = insn_3a[20];
505                                 dc__wr_req_3a = ~insn_3a[20];
506                         end
507                         `LSRH_BASEWB: begin end
508                         `LSRH_WBFLUSH: begin end
509                         default: begin end
510                         endcase
511                 end
512                 `DECODE_LDRSTR_UNDEFINED: begin end
513                 `DECODE_LDRSTR: if(!bubble_3a) begin
514                         addr = insn_3a[23] ? op0_3a + op1_3a : op0_3a - op1_3a; /* up/down select */
515                         raddr = insn_3a[24] ? addr : op0_3a; /* pre/post increment */
516                         dc__addr_3a = raddr;
517                         dc__data_size_3a = insn_3a[22] ? 3'b001 : 3'b100;
518                         case (lsr_state)
519                         `LSR_MEMIO: begin
520                                 dc__rd_req_3a = insn_3a[20] /* L */ || insn_3a[22] /* B */;
521                                 dc__wr_req_3a = !insn_3a[20] /* L */ && !insn_3a[22]/* B */;
522                         end
523                         `LSR_STRB_WR:
524                                 dc__wr_req_3a = 1;
525                         `LSR_BASEWB: begin end
526                         `LSR_WBFLUSH: begin end
527                         default: begin end
528                         endcase
529                 end
530                 `DECODE_LDMSTM: if (!bubble_3a) begin
531                         dc__data_size_3a = 3'b100;
532                         case (lsm_state)
533                         `LSM_SETUP:
534                                 offset = 6'b0;
535                         `LSM_MEMIO: begin
536                                 dc__rd_req_3a = insn_3a[20];
537                                 dc__wr_req_3a = ~insn_3a[20];
538                                 offset = prev_offset + 6'h4;
539                                 offset_sel = insn_3a[24] ? offset : prev_offset;
540                                 raddr = insn_3a[23] ? op0_3a + {26'b0, offset_sel} : op0_3a - {26'b0, offset_sel};
541                                 dc__addr_3a = raddr;
542                         end
543                         `LSM_BASEWB: begin end
544                         `LSM_WBFLUSH: begin end
545                         default: begin end
546                         endcase
547                 end
548                 `DECODE_LDCSTC: begin end
549                 `DECODE_CDP: begin end
550                 `DECODE_MRCMCR: begin end
551                 default: begin end
552                 endcase
553         end
554         
555         /* Bus data control logic. */
556         always @(*)
557         begin
558                 dc__wr_data_3a = 32'hxxxxxxxx;
559                 
560                 casez(insn_3a)
561                 `DECODE_ALU_SWP: if(!bubble_3a)
562                         if (swp_state == `SWP_WRITING)
563                                 dc__wr_data_3a = insn_3a[22] ? {4{op1_3a[7:0]}} : op1_3a;
564                 `DECODE_ALU_MULT: begin end
565                 `DECODE_ALU_HDATA_REG,
566                 `DECODE_ALU_HDATA_IMM: if(!bubble_3a)
567                         case(insn_3a[6:5])
568                         2'b01: /* unsigned half */
569                                 dc__wr_data_3a = {2{op2_3a[15:0]}}; /* XXX need to store halfword */
570                         2'b10: /* signed byte */
571                                 dc__wr_data_3a = {4{op2_3a[7:0]}};
572                         2'b11: /* signed half */
573                                 dc__wr_data_3a = {2{op2_3a[15:0]}};
574                         default: begin end
575                         endcase
576                 `DECODE_LDRSTR_UNDEFINED: begin end
577                 `DECODE_LDRSTR: if(!bubble_3a) begin
578                         dc__wr_data_3a = insn_3a[22] ? {24'h0, {op2_3a[7:0]}} : op2_3a;
579                         if (lsr_state == `LSR_STRB_WR)
580                                 case (dc__addr_3a[1:0])
581                                 2'b00: dc__wr_data_3a = {rd_data_latch[31:8], op2_3a[7:0]};
582                                 2'b01: dc__wr_data_3a = {rd_data_latch[31:16], op2_3a[7:0], rd_data_latch[7:0]};
583                                 2'b10: dc__wr_data_3a = {rd_data_latch[31:24], op2_3a[7:0], rd_data_latch[15:0]};
584                                 2'b11: dc__wr_data_3a = {op2_3a[7:0], rd_data_latch[23:0]};
585                                 endcase
586                 end
587                 `DECODE_LDMSTM: if (!bubble_3a)
588                         if (lsm_state == `LSM_MEMIO)
589                                 dc__wr_data_3a = (cur_reg == 4'hF) ? (pc_3a + 12) : rf__rdata_3_3a;
590                 `DECODE_LDCSTC: begin end
591                 `DECODE_CDP: begin end
592                 `DECODE_MRCMCR: begin end
593                 default: begin end
594                 endcase
595         end
596         
597         /* LDM/STM register control logic. */
598         always @(posedge clk)
599                 if (!dc__rw_wait_3a || lsm_state != `LSM_MEMIO)
600                 begin
601                         prev_reg <= cur_reg;
602                         regs <= next_regs;
603                 end
604         
605         always @(*)
606         begin
607                 rf__read_3_3a = 4'hx;
608                 cur_reg = prev_reg;
609                 next_regs = regs;
610                 
611                 casez(insn_3a)
612                 `DECODE_LDMSTM: if(!bubble_3a) begin
613                         case(lsm_state)
614                         `LSM_SETUP:
615                                 next_regs = insn_3a[23] /* U */ ? op1_3a[15:0] : {op1_3a[0], op1_3a[1], op1_3a[2], op1_3a[3], op1_3a[4], op1_3a[5], op1_3a[6], op1_3a[7],
616                                                                                op1_3a[8], op1_3a[9], op1_3a[10], op1_3a[11], op1_3a[12], op1_3a[13], op1_3a[14], op1_3a[15]};
617                         `LSM_MEMIO: begin
618                                 casez(regs)
619                                 16'b???????????????1: begin
620                                         cur_reg = 4'h0;
621                                         next_regs = {regs[15:1], 1'b0};
622                                 end
623                                 16'b??????????????10: begin
624                                         cur_reg = 4'h1;
625                                         next_regs = {regs[15:2], 2'b0};
626                                 end
627                                 16'b?????????????100: begin
628                                         cur_reg = 4'h2;
629                                         next_regs = {regs[15:3], 3'b0};
630                                 end
631                                 16'b????????????1000: begin
632                                         cur_reg = 4'h3;
633                                         next_regs = {regs[15:4], 4'b0};
634                                 end
635                                 16'b???????????10000: begin
636                                         cur_reg = 4'h4;
637                                         next_regs = {regs[15:5], 5'b0};
638                                 end
639                                 16'b??????????100000: begin
640                                         cur_reg = 4'h5;
641                                         next_regs = {regs[15:6], 6'b0};
642                                 end
643                                 16'b?????????1000000: begin
644                                         cur_reg = 4'h6;
645                                         next_regs = {regs[15:7], 7'b0};
646                                 end
647                                 16'b????????10000000: begin
648                                         cur_reg = 4'h7;
649                                         next_regs = {regs[15:8], 8'b0};
650                                 end
651                                 16'b???????100000000: begin
652                                         cur_reg = 4'h8;
653                                         next_regs = {regs[15:9], 9'b0};
654                                 end
655                                 16'b??????1000000000: begin
656                                         cur_reg = 4'h9;
657                                         next_regs = {regs[15:10], 10'b0};
658                                 end
659                                 16'b?????10000000000: begin
660                                         cur_reg = 4'hA;
661                                         next_regs = {regs[15:11], 11'b0};
662                                 end
663                                 16'b????100000000000: begin
664                                         cur_reg = 4'hB;
665                                         next_regs = {regs[15:12], 12'b0};
666                                 end
667                                 16'b???1000000000000: begin
668                                         cur_reg = 4'hC;
669                                         next_regs = {regs[15:13], 13'b0};
670                                 end
671                                 16'b??10000000000000: begin
672                                         cur_reg = 4'hD;
673                                         next_regs = {regs[15:14], 14'b0};
674                                 end
675                                 16'b?100000000000000: begin
676                                         cur_reg = 4'hE;
677                                         next_regs = {regs[15], 15'b0};
678                                 end
679                                 16'b1000000000000000: begin
680                                         cur_reg = 4'hF;
681                                         next_regs = 16'b0;
682                                 end
683                                 default: begin
684                                         cur_reg = 4'hx;
685                                         next_regs = 16'b0;
686                                 end
687                                 endcase
688                                 cur_reg = insn_3a[23] ? cur_reg : 4'hF - cur_reg;
689                                 
690                                 rf__read_3_3a = cur_reg;
691                         end
692                         `LSM_BASEWB: begin end
693                         `LSM_WBFLUSH: begin end
694                         default: begin end
695                         endcase
696                 end
697                 endcase
698         end
699         
700         always @(*)
701         begin
702                 do_rd_data_latch = 0;
703                 
704                 next_outbubble = bubble_3a;
705                 
706                 lsrh_rddata = 32'hxxxxxxxx;
707                 lsrh_rddata_s1 = 16'hxxxx;
708                 lsrh_rddata_s2 = 8'hxx;
709                 next_swp_oldval = swp_oldval;
710                 
711                 align_s1 = 32'hxxxxxxxx;
712                 align_s2 = 32'hxxxxxxxx;
713                 align_rddata = 32'hxxxxxxxx;
714
715                 /* XXX shit not given about endianness */
716                 casez(insn_3a)
717                 `DECODE_ALU_SWP: if(!bubble_3a) begin
718                         next_outbubble = dc__rw_wait_3a;
719                         case(swp_state)
720                         `SWP_READING:
721                                 if(!dc__rw_wait_3a)
722                                         next_swp_oldval = dc__rd_data_3a;
723                         `SWP_WRITING: begin end
724                         default: begin end
725                         endcase
726                 end
727                 `DECODE_ALU_MULT: begin
728                         next_outbubble = bubble_3a;     /* XXX workaround for Xilinx bug */
729                 end
730                 `DECODE_ALU_HDATA_REG,
731                 `DECODE_ALU_HDATA_IMM: if(!bubble_3a) begin
732                         next_outbubble = dc__rw_wait_3a;
733                         
734                         /* rotate to correct position */
735                         case(insn_3a[6:5])
736                         2'b01: begin /* unsigned half */
737                                 lsrh_rddata = {16'b0, raddr[1] ? dc__rd_data_3a[31:16] : dc__rd_data_3a[15:0]};
738                         end
739                         2'b10: begin /* signed byte */
740                                 lsrh_rddata_s1 = raddr[1] ? dc__rd_data_3a[31:16] : dc__rd_data_3a[15:0];
741                                 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
742                                 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
743                         end
744                         2'b11: begin /* signed half */
745                                 lsrh_rddata = raddr[1] ? {{16{dc__rd_data_3a[31]}}, dc__rd_data_3a[31:16]} : {{16{dc__rd_data_3a[15]}}, dc__rd_data_3a[15:0]};
746                         end
747                         default: begin
748                                 lsrh_rddata = 32'hxxxxxxxx;
749                         end
750                         endcase
751
752                         case(lsrh_state)
753                         `LSRH_MEMIO: begin end
754                         `LSRH_BASEWB:
755                                 next_outbubble = 1'b0;
756                         `LSRH_WBFLUSH: begin end
757                         default: begin end
758                         endcase
759                 end
760                 `DECODE_LDRSTR_UNDEFINED: begin end
761                 `DECODE_LDRSTR: if(!bubble_3a) begin
762                         next_outbubble = dc__rw_wait_3a;
763                         /* rotate to correct position */
764                         align_s1 = raddr[1] ? {dc__rd_data_3a[15:0], dc__rd_data_3a[31:16]} : dc__rd_data_3a;
765                         align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
766                         /* select byte or word */
767                         align_rddata = insn_3a[22] ? {24'b0, align_s2[7:0]} : align_s2;
768                         case(lsr_state)
769                         `LSR_MEMIO:
770                                 if (insn_3a[22] /* B */ && !insn_3a[20] /* L */)
771                                         do_rd_data_latch = 1;
772                         `LSR_STRB_WR: begin end
773                         `LSR_BASEWB:
774                                 next_outbubble = 0;
775                         `LSR_WBFLUSH: begin end
776                         default: begin end
777                         endcase
778                 end
779                 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
780                 `DECODE_LDMSTM: if(!bubble_3a) begin
781                         next_outbubble = dc__rw_wait_3a;
782                         case(lsm_state)
783                         `LSM_SETUP: begin end
784                         `LSM_MEMIO: begin end
785                         `LSM_BASEWB:
786                                 next_outbubble = 0;
787                         `LSM_WBFLUSH: begin end
788                         default: $stop;
789                         endcase
790                 end
791                 `DECODE_LDCSTC: begin end
792                 `DECODE_CDP: if(!bubble_3a) begin
793                         if (cp_busy) begin
794                                 next_outbubble = 1;
795                         end
796                 end
797                 `DECODE_MRCMCR: if(!bubble_3a) begin
798                         if (cp_busy) begin
799                                 next_outbubble = 1;
800                         end
801                 end
802                 default: begin end
803                 endcase
804                 
805                 if ((flush || delayedflush) && !outstall)
806                         next_outbubble = 1'b1;
807         end
808 endmodule
This page took 0.19307 seconds and 4 git commands to generate.