Decode.v

   1 `include "ARM_Constants.v"
   2
   3 module Decode(
   4         input clk,
   5         input stall,
   6         input [31:0] insn,
   7         input [31:0] inpc,
   8         input [31:0] incpsr,
   9         input [31:0] inspsr,
  10         output reg [31:0] op0,
  11         output reg [31:0] op1,
  12         output reg [31:0] op2,
  13         output reg carry,
  14         output reg [31:0] outcpsr,
  15         output reg [31:0] outspsr,
  16
  17         output reg [3:0] read_0,
  18         output reg [3:0] read_1,
  19         output reg [3:0] read_2,
  20         input [31:0] rdata_0,
  21         input [31:0] rdata_1,
  22         input [31:0] rdata_2
  23         );
  24
  25         wire [31:0] regs0, regs1, regs2;
  26         reg [31:0] rpc;
  27         reg [31:0] op0_out, op1_out, op2_out;
  28         reg carry_out;
  29
  30         /* shifter stuff */
  31         wire [31:0] shift_oper;
  32         wire [31:0] shift_res;
  33         wire shift_cflag_out;
  34         wire [31:0] rotate_res;
  35
  36         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
  37         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
  38         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
  39
  40         IREALLYHATEARMSHIFT shift(.insn(insn),
  41                                   .operand(regs1),
  42                                   .reg_amt(regs2),
  43                                   .cflag_in(incpsr[`CPSR_C]),
  44                                   .res(shift_res),
  45                                   .cflag_out(shift_cflag_out));
  46
  47         SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
  48                               .amt(insn[11:8]),
  49                               .res(rotate_res));
  50
  51         always @(*)
  52                 casez (insn)
  53                 `DECODE_ALU_MULT,               /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
  54 //              `DECODE_ALU_MUL_LONG,           /* Multiply long */
  55                 `DECODE_ALU_MRS,                /* MRS (Transfer PSR to register) */
  56                 `DECODE_ALU_MSR,                /* MSR (Transfer register to PSR) */
  57                 `DECODE_ALU_MSR_FLAGS,          /* MSR (Transfer register or immediate to PSR, flag bits only) */
  58                 `DECODE_ALU_SWP,                /* Atomic swap */
  59                 `DECODE_ALU_BX,                 /* Branch and exchange */
  60                 `DECODE_ALU_HDATA_REG,          /* Halfword transfer - register offset */
  61                 `DECODE_ALU_HDATA_IMM,          /* Halfword transfer - register offset */
  62                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
  63                 `DECODE_LDRSTR,                 /* Single data transfer */
  64                 `DECODE_LDMSTM,                 /* Block data transfer */
  65                 `DECODE_BRANCH,                 /* Branch */
  66                 `DECODE_LDCSTC,                 /* Coprocessor data transfer */
  67                 `DECODE_CDP,                    /* Coprocessor data op */
  68                 `DECODE_SWI:                    /* SWI */
  69                         rpc = inpc + 8;
  70                 `DECODE_MRCMCR:                 /* Coprocessor register transfer */
  71                         rpc = inpc + 12;
  72                 `DECODE_ALU:                    /* ALU */
  73                         rpc = inpc + (insn[25] ? 8 : (insn[4] ? 12 : 8));
  74                 default:                        /* X everything else out */
  75                         rpc = 32'hxxxxxxxx;
  76                 endcase
  77
  78         always @(*) begin
  79                 read_0 = 4'hx;
  80                 read_1 = 4'hx;
  81                 read_2 = 4'hx;
  82
  83                 casez (insn)
  84                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
  85                 begin
  86                         read_0 = insn[15:12]; /* Rn */
  87                         read_1 = insn[3:0];   /* Rm */
  88                         read_2 = insn[11:8];  /* Rs */
  89                 end
  90                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
  91                 begin end
  92                 `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */
  93                         read_0 = insn[3:0];     /* Rm */
  94                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
  95                         read_0 = insn[3:0];     /* Rm */
  96                 `DECODE_ALU_SWP:        /* Atomic swap */
  97                 begin
  98                         read_0 = insn[19:16]; /* Rn */
  99                         read_1 = insn[3:0];   /* Rm */
 100                 end
 101                 `DECODE_ALU_BX:         /* Branch and exchange */
 102                         read_0 = insn[3:0];   /* Rn */
 103                 `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
 104                 begin
 105                         read_0 = insn[19:16];
 106                         read_1 = insn[3:0];
 107                         read_2 = insn[15:12];
 108                 end
 109                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
 110                 begin
 111                         read_0 = insn[19:16];
 112                         read_1 = insn[15:12];
 113                 end
 114                 `DECODE_ALU:            /* ALU */
 115                 begin
 116                         read_0 = insn[19:16]; /* Rn */
 117                         read_1 = insn[3:0];   /* Rm */
 118                         read_2 = insn[11:8];  /* Rs for shift */
 119                 end
 120                 `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */
 121                 begin end
 122                 `DECODE_LDRSTR:         /* Single data transfer */
 123                 begin
 124                         read_0 = insn[19:16]; /* Rn */
 125                         read_1 = insn[3:0];   /* Rm */
 126                         read_2 = insn[15:12];
 127                 end
 128                 `DECODE_LDMSTM:         /* Block data transfer */
 129                         read_0 = insn[19:16];
 130                 `DECODE_BRANCH:         /* Branch */
 131                 begin end
 132                 `DECODE_LDCSTC:         /* Coprocessor data transfer */
 133                         read_0 = insn[19:16];
 134                 `DECODE_CDP:            /* Coprocessor data op */
 135                 begin end
 136                 `DECODE_MRCMCR:         /* Coprocessor register transfer */
 137                         read_0 = insn[15:12];
 138                 `DECODE_SWI:            /* SWI */
 139                 begin end
 140                 default:
 141                         $display("Undecoded instruction");
 142                 endcase
 143         end
 144
 145         always @(*) begin
 146                 op0_out = 32'hxxxxxxxx;
 147                 op1_out = 32'hxxxxxxxx;
 148                 op2_out = 32'hxxxxxxxx;
 149                 carry_out = 1'bx;
 150
 151                 casez (insn)
 152                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
 153                 begin
 154                         op0_out = regs0;
 155                         op1_out = regs1;
 156                         op2_out = regs2;
 157                 end
 158                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
 159                 begin end
 160                 `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */
 161                         op0_out = regs0;
 162                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
 163                         if(insn[25]) begin     /* the constant case */
 164                                 op0_out = rotate_res;
 165                         end else begin
 166                                 op0_out = regs0;
 167                         end
 168                 `DECODE_ALU_SWP:        /* Atomic swap */
 169                 begin
 170                         op0_out = regs0;
 171                         op1_out = regs1;
 172                 end
 173                 `DECODE_ALU_BX:         /* Branch and exchange */
 174                         op0_out = regs0;
 175                 `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
 176                 begin
 177                         op0_out = regs0;
 178                         op1_out = regs1;
 179                         op2_out = regs2;
 180                 end
 181                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
 182                 begin
 183                         op0_out = regs0;
 184                         op1_out = {24'b0, insn[11:8], insn[3:0]};
 185                         op2_out = regs1;
 186                 end
 187                 `DECODE_ALU:            /* ALU */
 188                 begin
 189                         op0_out = regs0;
 190                         if(insn[25]) begin     /* the constant case */
 191                                 carry_out = incpsr[`CPSR_C];
 192                                 op1_out = rotate_res;
 193                         end else begin
 194                                 carry_out = shift_cflag_out;
 195                                 op1_out = shift_res;
 196                         end
 197                 end
 198                 `DECODE_LDRSTR:         /* Single data transfer */
 199                 begin
 200                         op0_out = regs0;
 201                         if(!insn[25] /* immediate */) begin
 202                                 op1_out = {20'b0, insn[11:0]};
 203                                 carry_out = incpsr[`CPSR_C];
 204                         end else begin
 205                                 op1_out = shift_res;
 206                                 carry_out = shift_cflag_out;
 207                         end
 208                         op2_out = regs2;
 209                 end
 210                 `DECODE_LDMSTM:         /* Block data transfer */
 211                 begin
 212                         op0_out = regs0;
 213                         op1_out = {16'b0, insn[15:0]};
 214                 end
 215                 `DECODE_BRANCH:         /* Branch */
 216                         op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
 217                 `DECODE_LDCSTC:         /* Coprocessor data transfer */
 218                 begin
 219                         op0_out = regs0;
 220                         op1_out = {24'b0, insn[7:0]};
 221                 end
 222                 `DECODE_CDP:            /* Coprocessor data op */
 223                 begin end
 224                 `DECODE_MRCMCR:         /* Coprocessor register transfer */
 225                         op0_out = regs0;
 226                 `DECODE_SWI:            /* SWI */
 227                 begin end
 228                 endcase
 229         end
 230
 231         always @ (posedge clk) begin
 232                 if (!stall)
 233                 begin
 234                         op0 <= op0_out;   /* Rn - always */
 235                         op1 <= op1_out; /* 'operand 2' - Rm */
 236                         op2 <= op2_out;   /* thirdedge - Rs */
 237                         carry <= carry_out;
 238                         outcpsr <= incpsr;
 239                         outspsr <= inspsr;
 240                 end
 241         end
 242
 243 endmodule
 244
 245 module IREALLYHATEARMSHIFT(
 246         input [31:0] insn,
 247         input [31:0] operand,
 248         input [31:0] reg_amt,
 249         input cflag_in,
 250         output reg [31:0] res,
 251         output reg cflag_out
 252 );
 253         wire [5:0] shift_amt;
 254         reg is_arith, is_rot;
 255         wire rshift_cout;
 256         wire [31:0] rshift_res;
 257
 258         assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
 259                                    : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
 260
 261         SuckLessShifter barrel(.oper(operand),
 262                                .carryin(cflag_in),
 263                                .amt(shift_amt),
 264                                .is_arith(is_arith),
 265                                .is_rot(is_rot),
 266                                .res(rshift_res),
 267                                .carryout(rshift_cout));
 268
 269         always @(*)
 270                 case (insn[6:5])
 271                 `SHIFT_LSL: begin
 272                         /* meaningless */
 273                         is_rot = 1'b0;
 274                         is_arith = 1'b0;
 275                 end
 276                 `SHIFT_LSR: begin
 277                         is_rot = 1'b0;
 278                         is_arith = 1'b0;
 279                 end
 280                 `SHIFT_ASR: begin
 281                         is_rot = 1'b0;
 282                         is_arith = 1'b1;
 283                 end
 284                 `SHIFT_ROR: begin
 285                         is_rot = 1'b1;
 286                         is_arith = 1'b0;
 287                 end
 288                 endcase
 289
 290         always @(*)
 291                 case (insn[6:5]) /* shift type */
 292                 `SHIFT_LSL:
 293                         {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
 294                 `SHIFT_LSR: begin
 295                         res = rshift_res;
 296                         cflag_out = rshift_cout;
 297                 end
 298                 `SHIFT_ASR: begin
 299                         res = rshift_res;
 300                         cflag_out = rshift_cout;
 301                 end
 302                 `SHIFT_ROR: begin
 303                         if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
 304                                 res = {cflag_in, operand[31:1]};
 305                                 cflag_out = operand[0];
 306                         end else begin
 307                                 res = rshift_res;
 308                                 cflag_out = rshift_cout;
 309                         end
 310                 end
 311                 endcase
 312 endmodule
 313
 314 module SuckLessShifter(
 315         input [31:0] oper,
 316         input carryin,
 317         input [5:0] amt,
 318         input is_arith,
 319         input is_rot,
 320         output wire [31:0] res,
 321         output wire carryout
 322 );
 323
 324         wire [32:0] stage1, stage2, stage3, stage4, stage5;
 325
 326         wire pushbits = is_arith & oper[31];
 327
 328         /* do a barrel shift */
 329         assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
 330         assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
 331         assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
 332         assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
 333         assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
 334         assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
 335
 336 endmodule
 337
 338 module SuckLessRotator(
 339         input [31:0] oper,
 340         input [3:0] amt,
 341         output wire [31:0] res
 342 );
 343
 344         wire [31:0] stage1, stage2, stage3;
 345         assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
 346         assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
 347         assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
 348         assign res    = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
 349
 350 endmodule
 351