Writeback.v

   1 module Writeback(
   2         input clk,
   3
   4         input inbubble,
   5
   6         input write_reg,
   7         input [3:0] write_num,
   8         input [31:0] write_data,
   9
  10         input [31:0] cpsr,
  11         input [31:0] spsr,
  12
  13         output reg regfile_write,
  14         output reg [3:0] regfile_write_reg,
  15         output reg [31:0] regfile_write_data,
  16
  17         output reg [31:0] outcpsr,
  18         output reg [31:0] outspsr,
  19
  20         output reg jmp,
  21         output reg [31:0] jmppc);
  22
  23         reg [31:0] last_outcpsr = 0, last_outspsr = 0;
  24
  25         always @(*)
  26                 if (inbubble)
  27                         outcpsr = last_outcpsr;
  28                 else
  29                         outcpsr = cpsr;
  30
  31         always @(*)
  32                 if (inbubble)
  33                         outspsr = last_outspsr;
  34                 else
  35                         outspsr = spsr;
  36
  37         always @(*)
  38         begin
  39                 regfile_write = 0;
  40                 regfile_write_reg = 4'hx;
  41                 regfile_write_data = 32'hxxxxxxxx;
  42                 jmp = 0;
  43                 jmppc = 32'h00000000;
  44                 if (!inbubble)
  45                 begin
  46                         if (write_reg && (write_num != 15))
  47                         begin
  48                                 regfile_write = 1;
  49                                 regfile_write_reg = write_num;
  50                                 regfile_write_data = write_data;
  51                         end else if (write_reg && (write_num == 15)) begin
  52                                 jmp = 1;
  53                                 jmppc = write_data;
  54                         end
  55                 end
  56         end
  57
  58         always @(posedge clk)
  59         begin
  60                 last_outspsr <= outspsr;
  61                 last_outcpsr <= outcpsr;
  62         end
  63 endmodule