system: Correct routing regressions from renames.
[firearm.git] / Fetch.v
1 module Fetch(
2         input              clk,
3         input              Nrst,
4         
5         output wire [31:0] ic__rd_addr_0a,
6         output wire        ic__rd_req_0a,
7         input              ic__rd_wait_0a,
8         input       [31:0] ic__rd_data_1a,
9         
10         input              stall_0a,
11         input              jmp_0a,
12         input       [31:0] jmppc_0a,
13         output reg         bubble_1a = 1,
14         output reg  [31:0] insn_1a = 0,
15         output reg  [31:0] pc_1a = 32'hFFFFFFFC);
16         
17         reg qjmp = 0;   /* A jump has been queued up while we were waiting. */
18         reg [31:0] qjmppc;
19         always @(posedge clk or negedge Nrst)
20                 if (!Nrst)
21                         qjmp <= 0;
22                 else if ((ic__rd_wait_0a || stall_0a) && jmp_0a)
23                         {qjmp,qjmppc} <= {jmp_0a, jmppc_0a};
24                 else if (!ic__rd_wait_0a && !stall_0a && qjmp)  /* It has already been intoed. */
25                         {qjmp,qjmppc} <= {1'b0, 32'hxxxxxxxx};
26         
27         reg [31:0] reqpc_0a;
28         
29         /* Output latch logic */
30         reg [31:0] insn_2a;
31         reg stall_1a;
32         always @(posedge clk or negedge Nrst)
33                 if (!Nrst) begin
34                         insn_2a <= 32'h00000000;
35                         stall_1a <= 0;
36                 end else begin
37                         insn_2a <= insn_1a;
38                         stall_1a <= stall_0a;
39                 end
40         
41         always @(*)
42                 if (stall_1a)
43                         insn_1a = insn_2a;
44                 else
45                         insn_1a = ic__rd_data_1a;
46         
47         assign ic__rd_addr_0a = reqpc_0a;
48         assign ic__rd_req_0a = 1;
49         
50         always @(posedge clk or negedge Nrst)
51                 if (!Nrst) begin
52                         bubble_1a <= 1;
53                         pc_1a <= 32'h00000000;
54                 end else if (!stall_0a) begin
55                         bubble_1a <= (jmp_0a || qjmp || ic__rd_wait_0a);
56                         pc_1a <= reqpc_0a;
57                 end
58         
59         always @(posedge clk or negedge Nrst)
60                 if (!Nrst)
61                         reqpc_0a <= 0;
62                 else if (!stall_0a && !ic__rd_wait_0a) begin
63                         if (qjmp)
64                                 reqpc_0a <= qjmppc;
65                         else if (jmp_0a)
66                                 reqpc_0a <= jmppc_0a;
67                         else
68                                 reqpc_0a <= reqpc_0a + 4;
69                 end
70 endmodule
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