memory.v: convert to state machines
[firearm.git] / Memory.v
1 `include "ARM_Constants.v"
2
3 module Memory(
4         input clk,
5         input Nrst,
6
7         /* bus interface */
8         output reg [31:0] busaddr,
9         output reg rd_req,
10         output reg wr_req,
11         input rw_wait,
12         output reg [31:0] wr_data,
13         input [31:0] rd_data,
14
15         /* regfile interface */
16         output reg [3:0] st_read,
17         input [31:0] st_data,
18         
19         /* stage inputs */
20         input inbubble,
21         input [31:0] pc,
22         input [31:0] insn,
23         input [31:0] op0,
24         input [31:0] op1,
25         input [31:0] op2,
26         input [31:0] spsr,
27         input [31:0] cpsr,
28         input write_reg,
29         input [3:0] write_num,
30         input [31:0] write_data,
31
32         /* outputs */
33         output reg outstall,
34         output reg outbubble,
35         output reg [31:0] outpc,
36         output reg [31:0] outinsn,
37         output reg out_write_reg = 1'b0,
38         output reg [3:0] out_write_num = 4'bxxxx,
39         output reg [31:0] out_write_data = 32'hxxxxxxxx,
40         output reg [31:0] out_spsr = 32'hxxxxxxxx,
41         output reg [31:0] out_cpsr = 32'hxxxxxxxx
42         );
43
44         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
45         reg [3:0] next_regsel, cur_reg, prev_reg;
46         reg next_writeback;
47         reg [31:0] align_s1, align_s2, align_rddata;
48
49         wire next_outbubble;    
50         wire next_write_reg;
51         wire [3:0] next_write_num;
52         wire [31:0] next_write_data;
53
54         reg [1:0] lsr_state = 2'b01, next_lsr_state;
55
56         reg [15:0] regs, next_regs;
57         reg [2:0] lsm_state = 3'b001, next_lsm_state;
58         reg [5:0] offset, prev_offset, offset_sel;
59
60         reg [31:0] swp_oldval, next_swp_oldval;
61         reg [1:0] swp_state = 2'b01, next_swp_state;
62
63         always @(posedge clk)
64         begin
65                 outpc <= pc;
66                 outinsn <= insn;
67                 outbubble <= next_outbubble;
68                 out_write_reg <= next_write_reg;
69                 out_write_num <= next_write_num;
70                 out_write_data <= next_write_data;
71                 regs <= next_regs;
72                 prev_reg <= cur_reg;
73                 prev_offset <= offset;
74                 prev_raddr <= raddr;
75                 out_cpsr <= next_outcpsr;
76                 out_spsr <= spsr;
77                 swp_state <= next_swp_state;
78         end
79
80         always @(*)
81         begin
82                 addr = 32'hxxxxxxxx;
83                 raddr = 32'hxxxxxxxx;
84                 rd_req = 1'b0;
85                 wr_req = 1'b0;
86                 wr_data = 32'hxxxxxxxx;
87                 busaddr = 32'hxxxxxxxx;
88                 outstall = 1'b0;
89                 next_write_reg = write_reg;
90                 next_write_num = write_num;
91                 next_write_data = write_data;
92                 next_outbubble = inbubble;
93                 outstall = 1'b0;
94                 next_regs = regs;
95                 offset = prev_offset;
96                 next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
97                 next_lsm_state = lsm_state;
98                 next_lsr_state = lsr_state;
99                 next_swp_oldval = swp_oldval;
100                 next_swp_state = swp_state;
101                 cur_reg = prev_reg;
102
103                 casez(insn)
104                 `DECODE_ALU_SWP: begin
105                         if(!inbubble) begin
106                                 outstall = rw_wait;
107                                 next_outbubble = rw_wait;
108                                 busaddr = {op0[31:2], 2'b0};
109                                 case(swp_state)
110                                 2'b01: begin
111                                         rd_req = 1'b1;
112                                         outstall = 1'b1;
113                                         if(!rw_wait) begin
114                                                 next_swp_state = 2'b10;
115                                                 next_swp_oldval = rd_data;
116                                         end
117                                 end
118                                 2'b10: begin
119                                         wr_req = 1'b1;
120                                         wr_data = op1;
121                                         next_write_reg = 1'b1;
122                                         next_write_num = insn[15:12];
123                                         next_write_data = swp_oldval;
124                                         if(!rw_wait)
125                                                 next_swp_state = 2'b01;
126                                 end
127                                 default: begin end
128                                 endcase
129                         end
130                 end
131                 `DECODE_LDRSTR_UNDEFINED: begin end
132                 `DECODE_LDRSTR: begin
133                         if (!inbubble) begin
134                                 next_outbubble = rw_wait;
135                                 outstall = rw_wait;
136                                 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
137                                 raddr = insn[24] ? op0 : addr; /* pre/post increment */
138                                 busaddr = {raddr[31:2], 2'b0};
139
140                                 /* rotate to correct position */
141                                 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
142                                 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
143                                 /* select byte or word */
144                                 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
145                                 if(!insn[20]) begin
146                                         wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
147                                 end
148                                 case(lsr_state)
149                                 2'b01: begin
150                                         rd_req = insn[20];
151                                         wr_req = ~insn[20];
152
153                                         if(insn[20]) begin
154                                                 next_write_reg = 1'b1;
155                                                 next_write_num = insn[15:12];
156                                                 next_write_data = align_rddata;
157                                         end
158
159                                         if(insn[21]) begin
160                                                 outstall = 1'b1;
161                                                 if(!rw_wait)
162                                                         next_lsr_state = 2'b10;
163                                         end
164                                 end
165                                 2'b10: begin
166                                         next_write_reg = 1'b1;
167                                         next_write_num = insn[19:16];
168                                         next_write_data = addr;
169                                         next_lsr_state = 2'b10;
170                                 end
171                                 default: begin end
172                                 endcase
173                         end
174                 end
175                 `DECODE_LDMSTM: begin
176                         outstall = rw_wait;
177                         next_outbubble = rw_wait;
178                         case(lsm_state)
179                         3'b001: begin
180 //                              next_regs = insn[23] ? op1[15:0] : op1[0:15];
181                                 /** verilator can suck my dick */
182                                 next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
183                                                                     op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
184                                 offset = 6'b0;
185                                 outstall = 1'b1;
186                                 next_lsm_state = 3'b010;
187                         end
188                         3'b010: begin
189                                 rd_req = insn[20];
190                                 wr_req = ~insn[20];
191                                 casez(regs)
192                                 16'b???????????????1: begin
193                                         cur_reg = 4'h0;
194                                         next_regs = {regs[15:1], 1'b0};
195                                 end
196                                 16'b??????????????10: begin
197                                         cur_reg = 4'h1;
198                                         next_regs = {regs[15:2], 2'b0};
199                                 end
200                                 16'b?????????????100: begin
201                                         cur_reg = 4'h2;
202                                         next_regs = {regs[15:3], 3'b0};
203                                 end
204                                 16'b????????????1000: begin
205                                         cur_reg = 4'h3;
206                                         next_regs = {regs[15:4], 4'b0};
207                                 end
208                                 16'b???????????10000: begin
209                                         cur_reg = 4'h4;
210                                         next_regs = {regs[15:5], 5'b0};
211                                 end
212                                 16'b??????????100000: begin
213                                         cur_reg = 4'h5;
214                                         next_regs = {regs[15:6], 6'b0};
215                                 end
216                                 16'b?????????1000000: begin
217                                         cur_reg = 4'h6;
218                                         next_regs = {regs[15:7], 7'b0};
219                                 end
220                                 16'b????????10000000: begin
221                                         cur_reg = 4'h7;
222                                         next_regs = {regs[15:8], 8'b0};
223                                 end
224                                 16'b???????100000000: begin
225                                         cur_reg = 4'h8;
226                                         next_regs = {regs[15:9], 9'b0};
227                                 end
228                                 16'b??????1000000000: begin
229                                         cur_reg = 4'h9;
230                                         next_regs = {regs[15:10], 10'b0};
231                                 end
232                                 16'b?????10000000000: begin
233                                         cur_reg = 4'hA;
234                                         next_regs = {regs[15:11], 11'b0};
235                                 end
236                                 16'b????100000000000: begin
237                                         cur_reg = 4'hB;
238                                         next_regs = {regs[15:12], 12'b0};
239                                 end
240                                 16'b???1000000000000: begin
241                                         cur_reg = 4'hC;
242                                         next_regs = {regs[15:13], 13'b0};
243                                 end
244                                 16'b??10000000000000: begin
245                                         cur_reg = 4'hD;
246                                         next_regs = {regs[15:14], 14'b0};
247                                 end
248                                 16'b?100000000000000: begin
249                                         cur_reg = 4'hE;
250                                         next_regs = {regs[15], 15'b0};
251                                 end
252                                 16'b1000000000000000: begin
253                                         cur_reg = 4'hF;
254                                         next_regs = 16'b0;
255                                 end
256                                 default: begin
257                                         cur_reg = 4'hx;
258                                         next_regs = 16'b0;
259                                 end
260                                 endcase
261                                 cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
262                                 if(cur_reg == 4'hF && insn[22]) begin
263                                         next_outcpsr = spsr;
264                                 end
265
266                                 if(rw_wait) begin
267                                         next_regs = regs;
268                                         cur_reg = prev_reg;
269                                         raddr = prev_raddr;
270                                 end
271                                 else begin
272                                         offset = prev_offset + 6'h4;
273                                         offset_sel = insn[24] ? offset : prev_offset;
274                                         raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
275                                         if(insn[20]) begin
276                                                 next_write_reg = 1'b1;
277                                                 next_write_num = cur_reg;
278                                                 next_write_data = rd_data;
279                                         end
280                                 end
281
282                                 st_read = cur_reg;
283                                 wr_data = st_data;
284                                 busaddr = {raddr[31:2], 2'b0};
285
286                                 outstall = 1'b1;
287
288                                 if(next_regs == 16'b0) begin
289                                         next_lsm_state = 3'b100;
290                                 end
291                         end
292                         3'b100: begin
293                                 next_write_reg = 1'b1;
294                                 next_write_num = insn[19:16];
295                                 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
296                                 next_lsm_state = 3'b001;
297                         end
298                         default: begin end
299                         endcase
300                 end
301                 default: begin end
302                 endcase
303         end
304 endmodule
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