1 `include "ARM_Constants.v"
8 output reg [31:0] busaddr,
12 output reg [31:0] wr_data,
15 /* regfile interface */
16 output reg [3:0] st_read,
19 /* Coprocessor interface */
32 input [3:0] write_num,
33 input [31:0] write_data,
38 output reg [31:0] outpc,
39 output reg [31:0] outinsn,
40 output reg out_write_reg = 1'b0,
41 output reg [3:0] out_write_num = 4'bxxxx,
42 output reg [31:0] out_write_data = 32'hxxxxxxxx
45 reg [31:0] addr, raddr, next_regdata;
46 reg [3:0] next_regsel, cur_reg, prev_reg;
47 reg next_writeback, next_notdone, next_inc_next;
48 reg [31:0] align_s1, align_s2, align_rddata;
52 wire [3:0] next_write_num;
53 wire [31:0] next_write_data;
55 reg [15:0] regs, next_regs;
56 reg started = 1'b0, next_started;
65 outbubble <= next_outbubble;
66 out_write_reg <= next_write_reg;
67 out_write_num <= next_write_num;
68 out_write_data <= next_write_data;
69 notdone <= next_notdone;
70 inc_next <= next_inc_next;
73 started <= next_started;
82 wr_data = 32'hxxxxxxxx;
83 busaddr = 32'hxxxxxxxx;
86 next_write_reg = write_reg;
87 next_write_num = write_num;
88 next_write_data = write_data;
90 next_outbubble = inbubble;
93 next_started = started;
97 `DECODE_LDRSTR_UNDEFINED: begin end
100 next_outbubble = rw_wait;
101 outstall = rw_wait | notdone;
103 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
104 raddr = insn[24] ? op0 : addr; /* pre/post increment */
105 busaddr = {raddr[31:2], 2'b0};
109 /* rotate to correct position */
110 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
111 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
112 /* select byte or word */
113 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
116 wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
118 else if(!inc_next) begin
119 next_write_reg = 1'b1;
120 next_write_num = insn[15:12];
121 next_write_data = align_rddata;
122 next_inc_next = 1'b1;
124 else if(insn[21]) begin
125 next_write_reg = 1'b1;
126 next_write_num = insn[19:16];
127 next_write_data = addr;
129 next_notdone = rw_wait & insn[20] & insn[21];
132 `DECODE_LDMSTM: begin
136 next_regs = op1[15:0];
139 else if(inc_next) begin
141 next_write_reg = 1'b1;
142 next_write_num = insn[19:16];
143 next_write_data = op0;
147 else if(rw_wait) begin
153 16'b???????????????1: begin
155 next_regs = regs & 16'b1111111111111110;
157 16'b??????????????10: begin
159 next_regs = regs & 16'b1111111111111100;
161 16'b?????????????100: begin
163 next_regs = regs & 16'b1111111111111000;
165 16'b????????????1000: begin
167 next_regs = regs & 16'b1111111111110000;
169 16'b???????????10000: begin
171 next_regs = regs & 16'b1111111111100000;
173 16'b??????????100000: begin
175 next_regs = regs & 16'b1111111111000000;
177 16'b?????????1000000: begin
179 next_regs = regs & 16'b1111111110000000;
181 16'b????????10000000: begin
183 next_regs = regs & 16'b1111111100000000;
185 16'b???????100000000: begin
187 next_regs = regs & 16'b1111111000000000;
189 16'b??????1000000000: begin
191 next_regs = regs & 16'b1111110000000000;
193 16'b?????10000000000: begin
195 next_regs = regs & 16'b1111100000000000;
197 16'b????100000000000: begin
199 next_regs = regs & 16'b1111000000000000;
201 16'b???1000000000000: begin
203 next_regs = regs & 16'b1110000000000000;
205 16'b??10000000000000: begin
207 next_regs = regs & 16'b1100000000000000;
209 16'b?100000000000000: begin
211 next_regs = regs & 16'b1000000000000000;
213 16'b1000000000000000: begin
222 next_inc_next = next_regs == 16'b0;
223 next_notdone = ~next_inc_next | (rw_wait & insn[20] & insn[21]);