Cleanup pass on Decode. We may have to revert this if Wilson cannot get a fix; in...
[firearm.git] / Decode.v
1 `include "ARM_Constants.v"
2
3 module Decode(
4         input clk,
5         input [31:0] insn,
6         input [31:0] inpc,
7         input [31:0] incpsr,
8         output reg [31:0] op0,
9         output reg [31:0] op1,
10         output reg [31:0] op2,
11         output reg carry,
12
13         output reg [3:0] read_0,
14         output reg [3:0] read_1,
15         output reg [3:0] read_2,
16         input [31:0] rdata_0,
17         input [31:0] rdata_1,
18         input [31:0] rdata_2
19         );
20
21         wire [31:0] regs0, regs1, regs2;
22         reg [31:0] rpc;
23         reg [31:0] op0_out, op1_out, op2_out;
24         reg carry_out;
25
26         /* shifter stuff */
27         wire [31:0] shift_oper;
28         wire [31:0] shift_res;
29         wire shift_cflag_out;
30         wire [31:0] rotate_res;
31
32         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
33         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
34         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
35
36         IREALLYHATEARMSHIFT shift(.insn(insn),
37                                   .operand(regs1),
38                                   .reg_amt(regs2),
39                                   .cflag_in(incpsr[`CPSR_C]),
40                                   .res(shift_res),
41                                   .cflag_out(shift_cflag_out));
42
43         SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
44                               .amt(insn[11:8]),
45                               .res(rotate_res));
46
47         always @(*)
48                 casez (insn)
49                 `DECODE_ALU_MULT,               /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
50 //              `DECODE_ALU_MUL_LONG,           /* Multiply long */
51                 `DECODE_ALU_MRS,                /* MRS (Transfer PSR to register) */
52                 `DECODE_ALU_MSR,                /* MSR (Transfer register to PSR) */
53                 `DECODE_ALU_MSR_FLAGS,          /* MSR (Transfer register or immediate to PSR, flag bits only) */
54                 `DECODE_ALU_SWP,                /* Atomic swap */
55                 `DECODE_ALU_BX,                 /* Branch and exchange */
56                 `DECODE_ALU_HDATA_REG,          /* Halfword transfer - register offset */
57                 `DECODE_ALU_HDATA_IMM,          /* Halfword transfer - register offset */
58                 `DECODE_LDRSTR_UNDEFINED,       /* Undefined. I hate ARM */
59                 `DECODE_LDRSTR,                 /* Single data transfer */
60                 `DECODE_LDMSTM,                 /* Block data transfer */
61                 `DECODE_BRANCH,                 /* Branch */
62                 `DECODE_LDCSTC,                 /* Coprocessor data transfer */
63                 `DECODE_CDP,                    /* Coprocessor data op */
64                 `DECODE_MRCMCR,                 /* Coprocessor register transfer */
65                 `DECODE_SWI:                    /* SWI */
66                         rpc = inpc - 8;
67                 `DECODE_ALU:                    /* ALU */
68                         rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
69                 default:                        /* X everything else out */
70                         rpc = 32'hxxxxxxxx;
71                 endcase
72         
73         always @(*) begin
74                 read_0 = 4'hx;
75                 read_1 = 4'hx;
76                 read_2 = 4'hx;
77                 
78                 op0_out = 32'hxxxxxxxx;
79                 op1_out = 32'hxxxxxxxx;
80                 op2_out = 32'hxxxxxxxx;
81                 carry_out = 1'bx;
82                 
83                 casez (insn)
84                 `DECODE_ALU_MULT:       /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
85                 begin
86                         read_0 = insn[15:12]; /* Rn */
87                         read_1 = insn[3:0];   /* Rm */
88                         read_2 = insn[11:8];  /* Rs */
89                         
90                         op0_out = regs0;
91                         op1_out = regs1;
92                         op2_out = regs2;
93                 end
94 //              `DECODE_ALU_MUL_LONG:   /* Multiply long */
95 //              begin
96 //                      read_0 = insn[11:8]; /* Rn */
97 //                      read_1 = insn[3:0];   /* Rm */
98 //                      read_2 = 4'b0;       /* anyus */
99 //
100 //                      op1_res = regs1;
101 //              end
102                 `DECODE_ALU_MRS:        /* MRS (Transfer PSR to register) */
103                 begin end
104                 `DECODE_ALU_MSR:        /* MSR (Transfer register to PSR) */
105                 begin
106                         read_0 = insn[3:0];     /* Rm */
107                         
108                         op0_out = regs0;
109                 end
110                 `DECODE_ALU_MSR_FLAGS:  /* MSR (Transfer register or immediate to PSR, flag bits only) */
111                 begin
112                         read_0 = insn[3:0];     /* Rm */
113                         
114                         if(insn[25]) begin     /* the constant case */
115                                 op0_out = rotate_res;
116                         end else begin
117                                 op0_out = regs0;
118                         end
119                 end
120                 `DECODE_ALU_SWP:        /* Atomic swap */
121                 begin
122                         read_0 = insn[19:16]; /* Rn */
123                         read_1 = insn[3:0];   /* Rm */
124                         
125                         op0_out = regs0;
126                         op1_out = regs1;
127                 end
128                 `DECODE_ALU_BX:         /* Branch and exchange */
129                 begin
130                         read_0 = insn[3:0];   /* Rn */
131                         
132                         op0_out = regs0;
133                 end
134                 `DECODE_ALU_HDATA_REG:  /* Halfword transfer - register offset */
135                 begin
136                         read_0 = insn[19:16];
137                         read_1 = insn[3:0];
138                         
139                         op0_out = regs0;
140                         op1_out = regs1;
141                 end
142                 `DECODE_ALU_HDATA_IMM:  /* Halfword transfer - immediate offset */
143                 begin
144                         read_0 = insn[19:16];
145                         
146                         op0_out = regs0;
147                         op1_out = {24'b0, insn[11:8], insn[3:0]};
148                 end
149                 `DECODE_ALU:            /* ALU */
150                 begin
151                         read_0 = insn[19:16]; /* Rn */
152                         read_1 = insn[3:0];   /* Rm */
153                         read_2 = insn[11:8];  /* Rs for shift */
154                         
155                         op0_out = regs0;
156                         if(insn[25]) begin     /* the constant case */
157                                 carry_out = incpsr[`CPSR_C];
158                                 op1_out = rotate_res;
159                         end else begin
160                                 carry_out = shift_cflag_out;
161                                 op1_out = shift_res;
162                         end
163                 end
164                 `DECODE_LDRSTR_UNDEFINED:       /* Undefined. I hate ARM */
165                 begin
166                         /* eat shit */
167                 end
168                 `DECODE_LDRSTR:         /* Single data transfer */
169                 begin
170                         read_0 = insn[19:16]; /* Rn */
171                         read_1 = insn[3:0];   /* Rm */
172                         
173                         op0_out = regs0;
174                         if(insn[25]) begin
175                                 op1_out = {20'b0, insn[11:0]};
176                                 carry_out = incpsr[`CPSR_C];
177                         end else begin
178                                 op1_out = shift_res;
179                                 carry_out = shift_cflag_out;
180                         end
181                 end
182                 `DECODE_LDMSTM:         /* Block data transfer */
183                 begin
184                         read_0 = insn[19:16];
185                         
186                         op0_out = regs0;
187                         op1_out = {16'b0, insn[15:0]};
188                 end
189                 `DECODE_BRANCH:         /* Branch */
190                 begin
191                         op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
192                 end
193                 `DECODE_LDCSTC:         /* Coprocessor data transfer */
194                 begin
195                         read_0 = insn[19:16];
196                         
197                         op0_out = regs0;
198                         op1_out = {24'b0, insn[7:0]};
199                 end
200                 `DECODE_CDP:            /* Coprocessor data op */
201                 begin
202                 end
203                 `DECODE_MRCMCR:         /* Coprocessor register transfer */
204                 begin
205                         read_0 = insn[15:12];
206                         
207                         op0_out = regs0;
208                 end
209                 `DECODE_SWI:            /* SWI */
210                 begin
211                 end
212                 default:
213                         $display("Undecoded instruction");
214                 endcase
215         end
216
217         
218         always @ (posedge clk) begin
219                 op0 <= op0_out;   /* Rn - always */
220                 op1 <= op1_out; /* 'operand 2' - Rm */
221                 op2 <= op2_out;   /* thirdedge - Rs */
222                 carry <= carry_out;
223         end
224
225 endmodule
226
227 module IREALLYHATEARMSHIFT(
228         input [31:0] insn,
229         input [31:0] operand,
230         input [31:0] reg_amt,
231         input cflag_in,
232         output reg [31:0] res,
233         output reg cflag_out
234 );
235         wire [5:0] shift_amt;
236         reg is_arith, is_rot;
237         wire rshift_cout;
238         wire [31:0] rshift_res;
239
240         assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
241                                    : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
242
243         SuckLessShifter barrel(.oper(operand),
244                                .carryin(cflag_in),
245                                .amt(shift_amt),
246                                .is_arith(is_arith),
247                                .is_rot(is_rot),
248                                .res(rshift_res),
249                                .carryout(rshift_cout));
250
251         always @(*)
252                 case (insn[6:5])
253                 `SHIFT_LSL: begin
254                         /* meaningless */
255                         is_rot = 1'b0;
256                         is_arith = 1'b0;
257                 end
258                 `SHIFT_LSR: begin
259                         is_rot = 1'b0;
260                         is_arith = 1'b0;
261                 end
262                 `SHIFT_ASR: begin
263                         is_rot = 1'b0;
264                         is_arith = 1'b1;
265                 end
266                 `SHIFT_ROR: begin
267                         is_rot = 1'b1;
268                         is_arith = 1'b0;
269                 end
270                 endcase
271
272         always @(*)
273                 case (insn[6:5]) /* shift type */
274                 `SHIFT_LSL:
275                         {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
276                 `SHIFT_LSR: begin
277                         res = rshift_res;
278                         cflag_out = rshift_cout;
279                 end
280                 `SHIFT_ASR: begin
281                         res = rshift_res;
282                         cflag_out = rshift_cout;
283                 end
284                 `SHIFT_ROR: begin
285                         if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
286                                 res = {cflag_in, operand[31:1]};
287                                 cflag_out = operand[0];
288                         end else begin
289                                 res = rshift_res;
290                                 cflag_out = rshift_cout;
291                         end
292                 end
293                 endcase
294 endmodule
295
296 module SuckLessShifter(
297         input [31:0] oper,
298         input carryin,
299         input [5:0] amt,
300         input is_arith,
301         input is_rot,
302         output wire [31:0] res,
303         output wire carryout
304 );
305
306         wire [32:0] stage1, stage2, stage3, stage4, stage5;
307
308         wire pushbits = is_arith & oper[31];
309
310         /* do a barrel shift */
311         assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
312         assign stage2 = amt[4] ? {is_rot ? stage1[16:1] : {16{pushbits}}, stage1[32:17], stage1[16]} : stage1;
313         assign stage3 = amt[3] ? {is_rot ? stage2[8:1] : {8{pushbits}}, stage2[32:9], stage2[8]} : stage2;
314         assign stage4 = amt[2] ? {is_rot ? stage3[4:1] : {4{pushbits}}, stage3[32:5], stage3[4]} : stage3;
315         assign stage5 = amt[1] ? {is_rot ? stage4[2:1] : {2{pushbits}}, stage4[32:3], stage4[2]} : stage4;
316         assign {res, carryout} = amt[0] ? {is_rot ? stage5[1] : pushbits, stage5[32:2], stage5[1]} : stage5;
317
318 endmodule
319
320 module SuckLessRotator(
321         input [31:0] oper,
322         input [3:0] amt,
323         output wire [31:0] res
324 );
325
326         wire [31:0] stage1, stage2, stage3;
327         assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
328         assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
329         assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
330         assign res    = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
331
332 endmodule
333
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