Decode.v

   1 `include "ARM_Constants.v"
   2
   3 module Decode(
   4         input clk,
   5         input [31:0] insn,
   6         input [31:0] inpc,
   7         input [31:0] incpsr,
   8         output reg [31:0] op0,
   9         output reg [31:0] op1,
  10         output reg [31:0] op2,
  11         output reg carry,
  12
  13         output [3:0] read_0,
  14         output [3:0] read_1,
  15         output [3:0] read_2,
  16         input [31:0] rdata_0,
  17         input [31:0] rdata_1,
  18         input [31:0] rdata_2
  19         );
  20
  21         wire [31:0] regs0, regs1, regs2, rpc;
  22         wire [31:0] op0_out, op1_out, op2_out;
  23         wire carry_out;
  24
  25         /* shifter stuff */
  26         wire [31:0] shift_oper;
  27         wire [31:0] shift_res;
  28         wire shift_cflag_out;
  29         wire [31:0] rotate_res;
  30
  31         assign regs0 = (read_0 == 4'b1111) ? rpc : rdata_0;
  32         assign regs1 = (read_1 == 4'b1111) ? rpc : rdata_1;
  33         assign regs2 = rdata_2; /* use regs2 for things that cannot be r15 */
  34
  35         IREALLYHATEARMSHIFT blowme(.insn(insn),
  36                                    .operand(regs1),
  37                                    .reg_amt(regs2),
  38                                    .cflag_in(incpsr[`CPSR_C]),
  39                                    .res(shift_res),
  40                                    .cflag_out(shift_cflag_out));
  41
  42         SuckLessRotator whirr(.oper({24'b0, insn[7:0]}),
  43                               .amt(insn[11:8]),
  44                               .res(rotate_res));
  45
  46         always @(*)
  47                 casez (insn)
  48                 32'b????000000??????????????1001????,   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
  49 //              32'b????00001???????????????1001????,   /* Multiply long */
  50                 32'b????00010?001111????000000000000,   /* MRS (Transfer PSR to register) */
  51                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
  52                 32'b????00?10?1010001111????????????,   /* MSR (Transfer register or immediate to PSR, flag bits only) */
  53                 32'b????00010?00????????00001001????,   /* Atomic swap */
  54                 32'b????000100101111111111110001????,   /* Branch and exchange */
  55                 32'b????000??0??????????00001??1????,   /* Halfword transfer - register offset */
  56                 32'b????000??1??????????00001??1????,   /* Halfword transfer - register offset */
  57                 32'b????011????????????????????1????,   /* Undefined. I hate ARM */
  58                 32'b????01??????????????????????????,   /* Single data transfer */
  59                 32'b????100?????????????????????????,   /* Block data transfer */
  60                 32'b????101?????????????????????????,   /* Branch */
  61                 32'b????110?????????????????????????,   /* Coprocessor data transfer */
  62                 32'b????1110???????????????????0????,   /* Coprocessor data op */
  63                 32'b????1110???????????????????1????,   /* Coprocessor register transfer */
  64                 32'b????1111????????????????????????:   /* SWI */
  65                         rpc = inpc - 8;
  66                 32'b????00??????????????????????????:   /* ALU */
  67                         rpc = inpc - (insn[25] ? 8 : (insn[4] ? 12 : 8));
  68                 default:                                /* X everything else out */
  69                         rpc = 32'hxxxxxxxx;
  70                 endcase
  71
  72         always @(*) begin
  73                 read_0 = 4'hx;
  74                 read_1 = 4'hx;
  75                 read_2 = 4'hx;
  76
  77                 casez (insn)
  78                 32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
  79                 begin
  80                         read_0 = insn[15:12]; /* Rn */
  81                         read_1 = insn[3:0];   /* Rm */
  82                         read_2 = insn[11:8];  /* Rs */
  83                 end
  84 //              32'b????00001???????????????1001????,   /* Multiply long */
  85 //                      read_0 = insn[11:8]; /* Rn */
  86 //                      read_1 = insn[3:0];   /* Rm */
  87 //                      read_2 = 4'b0;       /* anyus */
  88                 32'b????00010?001111????000000000000:   /* MRS (Transfer PSR to register) */
  89                 begin end
  90                 32'b????00010?101001111100000000????,   /* MSR (Transfer register to PSR) */
  91                 32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
  92                         read_0 = insn[3:0];     /* Rm */
  93                 32'b????00??????????????????????????:   /* ALU */
  94                 begin
  95                         read_0 = insn[19:16]; /* Rn */
  96                         read_1 = insn[3:0];   /* Rm */
  97                         read_2 = insn[11:8];  /* Rs for shift */
  98                 end
  99                 32'b????00010?00????????00001001????:   /* Atomic swap */
 100                 begin
 101                         read_0 = insn[19:16]; /* Rn */
 102                         read_1 = insn[3:0];   /* Rm */
 103                 end
 104                 32'b????000100101111111111110001????:   /* Branch and exchange */
 105                         read_0 = insn[3:0];   /* Rn */
 106                 32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
 107                 begin
 108                         read_0 = insn[19:16];
 109                         read_1 = insn[3:0];
 110                 end
 111                 32'b????000??1??????????00001??1????:   /* Halfword transfer - immediate offset */
 112                 begin
 113                         read_0 = insn[19:16];
 114                 end
 115                 32'b????011????????????????????1????:   /* Undefined. I hate ARM */
 116                 begin end
 117                 32'b????01??????????????????????????:   /* Single data transfer */
 118                 begin
 119                         read_0 = insn[19:16]; /* Rn */
 120                         read_1 = insn[3:0];   /* Rm */
 121                 end
 122                 32'b????100?????????????????????????:   /* Block data transfer */
 123                         read_0 = insn[19:16];
 124                 32'b????101?????????????????????????:   /* Branch */
 125                 begin end
 126                 32'b????110?????????????????????????:   /* Coprocessor data transfer */
 127                         read_0 = insn[19:16];
 128                 32'b????1110???????????????????0????:   /* Coprocessor data op */
 129                 begin end
 130                 32'b????1110???????????????????1????:   /* Coprocessor register transfer */
 131                         read_0 = insn[15:12];
 132                 32'b????1111????????????????????????:   /* SWI */
 133                 begin end
 134                 default:
 135                         $display("Undecoded instruction");
 136                 endcase
 137         end
 138
 139         always @(*) begin
 140                 op0_out = 32'hxxxxxxxx;
 141                 op1_out = 32'hxxxxxxxx;
 142                 op2_out = 32'hxxxxxxxx;
 143                 carry_out = 1'bx;
 144                 casez (insn)
 145                 32'b????000000??????????????1001????: begin /* Multiply */
 146                         op0_out = regs0;
 147                         op1_out = regs1;
 148                         op2_out = regs2;
 149                 end
 150 //              32'b????00001???????????????1001????: begin /* Multiply long */
 151 //                      op1_res = regs1;
 152 //              end
 153                 32'b????00010?001111????000000000000: begin /* MRS (Transfer PSR to register) */
 154                 end
 155                 32'b????00010?101001111100000000????: begin /* MSR (Transfer register to PSR) */
 156                         op0_out = regs0;
 157                 end
 158                 32'b????00?10?1010001111????????????: begin /* MSR (Transfer register or immediate to PSR, flag bits only) */
 159                         if(insn[25]) begin     /* the constant case */
 160                                 op0_out = rotate_res;
 161                         end else begin
 162                                 op0_out = regs0;
 163                         end
 164                 end
 165                 32'b????00??????????????????????????: begin /* ALU */
 166                         op0_out = regs0;
 167                         if(insn[25]) begin     /* the constant case */
 168                                 carry_out = incpsr[`CPSR_C];
 169                                 op1_out = rotate_res;
 170                         end else begin
 171                                 carry_out = shift_cflag_out;
 172                                 op1_out = shift_res;
 173                         end
 174                 end
 175                 32'b????00010?00????????00001001????: begin /* Atomic swap */
 176                         op0_out = regs0;
 177                         op1_out = regs1;
 178                 end
 179                 32'b????000100101111111111110001????: begin /* Branch and exchange */
 180                         op0_out = regs0;
 181                 end
 182                 32'b????000??0??????????00001??1????: begin /* Halfword transfer - register offset */
 183                         op0_out = regs0;
 184                         op1_out = regs1;
 185                 end
 186                 32'b????000??1??????????00001??1????: begin /* Halfword transfer - immediate offset */
 187                         op0_out = regs0;
 188                         op1_out = {24'b0, insn[11:8], insn[3:0]};
 189                 end
 190                 32'b????011????????????????????1????: begin /* Undefined. I hate ARM */
 191                         /* eat shit */
 192                 end
 193                 32'b????01??????????????????????????: begin /* Single data transfer */
 194                         op0_out = regs0;
 195                         if(insn[25]) begin
 196                                 op1_out = {20'b0, insn[11:0]};
 197                                 carry_out = incpsr[`CPSR_C];
 198                         end else begin
 199                                 op1_out = shift_res;
 200                                 carry_out = shift_cflag_out;
 201                         end
 202                 end
 203                 32'b????100?????????????????????????: begin /* Block data transfer */
 204                         op0_out = regs0;
 205                         op1_out = {16'b0, insn[15:0]};
 206                 end
 207                 32'b????101?????????????????????????: begin /* Branch */
 208                         op0_out = {{6{insn[23]}}, insn[23:0], 2'b0};
 209                 end
 210                 32'b????110?????????????????????????: begin /* Coprocessor data transfer */
 211                         op0_out = regs0;
 212                         op1_out = {24'b0, insn[7:0]};
 213                 end
 214                 32'b????1110???????????????????0????: begin /* Coprocessor data op */
 215                 end
 216                 32'b????1110???????????????????1????: begin /* Coprocessor register transfer */
 217                         op0_out = regs0;
 218                 end
 219                 32'b????1111????????????????????????: begin /* SWI */
 220                 end
 221                 default: begin end
 222                 endcase
 223         end
 224
 225         always @ (posedge clk) begin
 226                 op0 <= op0_out;   /* Rn - always */
 227                 op1 <= op1_out; /* 'operand 2' - Rm */
 228                 op2 <= op2_out;   /* thirdedge - Rs */
 229                 carry <= carry_out;
 230         end
 231
 232 endmodule
 233
 234 module IREALLYHATEARMSHIFT(
 235         input [31:0] insn,
 236         input [31:0] operand,
 237         input [31:0] reg_amt,
 238         input cflag_in,
 239         output [31:0] res,
 240         output cflag_out
 241 );
 242         wire [5:0] shift_amt;
 243         wire rshift_cout, is_arith, is_rot;
 244         wire [31:0] rshift_res;
 245
 246         assign shift_amt = insn[4] ? {|reg_amt[7:5], reg_amt[4:0]}     /* reg-specified shift */
 247                                    : {insn[11:7] == 5'b0, insn[11:7]}; /* immediate shift */
 248
 249         SuckLessShifter biteme(.oper(operand),
 250                                .carryin(cflag_in),
 251                                .amt(shift_amt),
 252                                .is_arith(is_arith),
 253                                .is_rot(is_rot),
 254                                .res(rshift_res),
 255                                .carryout(rshift_cout));
 256
 257         always @(*)
 258                 case (insn[6:5])
 259                 `SHIFT_LSL: begin
 260                         /* meaningless */
 261                         is_rot = 1'b0;
 262                         is_arith = 1'b0;
 263                 end
 264                 `SHIFT_LSR: begin
 265                         is_rot = 1'b0;
 266                         is_arith = 1'b0;
 267                 end
 268                 `SHIFT_ASR: begin
 269                         is_rot = 1'b0;
 270                         is_arith = 1'b1;
 271                 end
 272                 `SHIFT_ROR: begin
 273                         is_rot = 1'b1;
 274                         is_arith = 1'b0;
 275                 end
 276                 endcase
 277
 278         always @(*)
 279                 case (insn[6:5]) /* shift type */
 280                 `SHIFT_LSL:
 281                         {cflag_out, res} = {cflag_in, operand} << {insn[4] & shift_amt[5], shift_amt[4:0]};
 282                 `SHIFT_LSR: begin
 283                         res = rshift_res;
 284                         cflag_out = rshift_cout;
 285                 end
 286                 `SHIFT_ASR: begin
 287                         res = rshift_res;
 288                         cflag_out = rshift_cout;
 289                 end
 290                 `SHIFT_ROR: begin
 291                         if(!insn[4] && shift_amt[4:0] == 5'b0) begin /* RRX x.x */
 292                                 res = {cflag_in, operand[31:1]};
 293                                 cflag_out = operand[0];
 294                         end else begin
 295                                 res = rshift_res;
 296                                 cflag_out = rshift_cout;
 297                         end
 298                 end
 299                 endcase
 300 endmodule
 301
 302 module SuckLessShifter(
 303         input [31:0] oper,
 304         input carryin,
 305         input [5:0] amt,
 306         input is_arith,
 307         input is_rot,
 308         output [31:0] res,
 309         output carryout
 310 );
 311
 312         wire [32:0] stage1, stage2, stage3, stage4, stage5;
 313
 314         wire pushbits = is_arith & oper[31];
 315
 316         /* do a barrel shift */
 317         assign stage1 = amt[5] ? {is_rot ? oper : {32{pushbits}}, oper[31]} : {oper, carryin};
 318         assign stage2 = amt[4] ? {is_rot ? stage1[15:0] : {16{pushbits}}, stage1[31:16], stage1[15]} : stage1;
 319         assign stage3 = amt[3] ? {is_rot ? stage2[7:0] : {8{pushbits}}, stage2[31:8], stage2[7]} : stage2;
 320         assign stage4 = amt[2] ? {is_rot ? stage3[3:0] : {4{pushbits}}, stage3[31:4], stage3[3]} : stage3;
 321         assign stage5 = amt[1] ? {is_rot ? stage4[1:0] : {2{pushbits}}, stage4[31:2], stage4[1]} : stage4;
 322         assign {res, carryout} = amt[0] ? {is_rot ? stage5[0] : pushbits, stage5[31:1], stage5[0]} : stage5;
 323
 324 endmodule
 325
 326 module SuckLessRotator(
 327         input [31:0] oper,
 328         input [3:0] amt,
 329         output [31:0] res
 330 );
 331
 332         wire [31:0] stage1, stage2, stage3;
 333         assign stage1 = amt[3] ? {oper[15:0], oper[31:16]} : oper;
 334         assign stage2 = amt[2] ? {stage1[7:0], stage1[31:8]} : stage1;
 335         assign stage3 = amt[1] ? {stage2[3:0], stage2[31:4]} : stage2;
 336         assign res    = amt[0] ? {stage3[1:0], stage3[31:2]} : stage3;
 337
 338 endmodule