1 `include "ARM_Constants.v"
3 `define SWP_READING 2'b01
4 `define SWP_WRITING 2'b10
6 `define LSRH_MEMIO 3'b001
7 `define LSRH_BASEWB 3'b010
8 `define LSRH_WBFLUSH 3'b100
10 `define LSR_MEMIO 4'b0001
11 `define LSR_STRB_WR 4'b0010
12 `define LSR_BASEWB 4'b0100
13 `define LSR_WBFLUSH 4'b1000
15 `define LSM_SETUP 4'b0001
16 `define LSM_MEMIO 4'b0010
17 `define LSM_BASEWB 4'b0100
18 `define LSM_WBFLUSH 4'b1000
28 output reg [31:0] busaddr,
32 output reg [31:0] wr_data,
34 output reg [2:0] data_size,
36 /* regfile interface */
37 output reg [3:0] st_read,
40 /* Coprocessor interface */
44 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
46 output reg [31:0] cp_write,
59 input [3:0] write_num,
60 input [31:0] write_data,
65 output reg [31:0] outpc,
66 output reg [31:0] outinsn,
67 output reg out_write_reg = 1'b0,
68 output reg [3:0] out_write_num = 4'bxxxx,
69 output reg [31:0] out_write_data = 32'hxxxxxxxx,
70 output reg [31:0] outspsr = 32'hxxxxxxxx,
71 output reg [31:0] outcpsr = 32'hxxxxxxxx,
72 output reg outcpsrup = 1'hx
75 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
78 reg [3:0] next_regsel, cur_reg, prev_reg;
83 reg [3:0] next_write_num;
84 reg [31:0] next_write_data;
86 reg [3:0] lsr_state = 4'b0001, next_lsr_state;
87 reg [31:0] align_s1, align_s2, align_rddata;
89 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
90 reg [31:0] lsrh_rddata;
91 reg [15:0] lsrh_rddata_s1;
92 reg [7:0] lsrh_rddata_s2;
94 reg [15:0] regs, next_regs;
95 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
96 reg [5:0] offset, prev_offset, offset_sel;
98 reg [31:0] swp_oldval, next_swp_oldval;
99 reg [1:0] swp_state = 2'b01, next_swp_state;
101 reg do_rd_data_latch;
102 reg [31:0] rd_data_latch = 32'hxxxxxxxx;
104 always @(posedge clk)
108 outbubble <= next_outbubble;
109 out_write_reg <= next_write_reg;
110 out_write_num <= next_write_num;
111 out_write_data <= next_write_data;
115 prev_offset <= offset;
117 outcpsr <= next_outcpsr;
119 outcpsrup <= next_outcpsrup;
120 swp_state <= next_swp_state;
121 lsm_state <= next_lsm_state;
122 lsr_state <= next_lsr_state;
123 lsrh_state <= next_lsrh_state;
124 if (do_rd_data_latch)
125 rd_data_latch <= rd_data;
129 reg delayedflush = 0;
130 always @(posedge clk)
131 if (flush && outstall /* halp! I can't do it now, maybe later? */)
133 else if (!outstall /* anything has been handled this time around */)
136 /* Drive the state machines and stall. */
140 next_lsm_state = lsm_state;
141 next_lsr_state = lsr_state;
142 next_lsrh_state = lsrh_state;
143 next_swp_state = swp_state;
145 `DECODE_ALU_SWP: if(!inbubble) begin
150 next_swp_state = `SWP_WRITING;
151 $display("SWP: read stage");
156 next_swp_state = `SWP_READING;
157 $display("SWP: write stage");
161 next_swp_state = 2'bxx;
165 `DECODE_ALU_MULT: begin end
166 `DECODE_ALU_HDATA_REG,
167 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
171 if(insn[21] | !insn[24]) begin
174 next_lsrh_state = `LSRH_BASEWB;
177 if (flush) /* special case! */ begin
179 next_lsrh_state = `LSRH_MEMIO;
182 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
186 next_lsrh_state = `LSRH_WBFLUSH;
190 next_lsrh_state = `LSRH_MEMIO;
194 next_lsrh_state = 3'bxxx;
198 `DECODE_LDRSTR_UNDEFINED: begin end
199 `DECODE_LDRSTR: if(!inbubble) begin
204 next_lsr_state = `LSR_MEMIO;
205 if (insn[22] /* B */ && !insn[20] /* L */) begin /* i.e., strb */
208 next_lsr_state = `LSR_STRB_WR;
209 end else if (insn[21] /* W */ || !insn[24] /* P */) begin /* writeback needed */
212 next_lsr_state = `LSR_BASEWB;
217 next_lsr_state = `LSR_MEMIO;
219 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
223 if(insn[21] /* W */ | !insn[24] /* P */) begin
225 next_lsr_state = `LSR_BASEWB;
226 end else if (!rw_wait)
227 next_lsr_state = `LSR_WBFLUSH;
228 $display("LDRSTR: Handling STRB");
232 next_lsr_state = `LSR_WBFLUSH;
236 next_lsr_state = `LSR_MEMIO;
240 next_lsr_state = 4'bxxxx;
243 $display("LDRSTR: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsr_state, next_lsr_state, outstall);
245 `DECODE_LDMSTM: if(!inbubble) begin
250 next_lsm_state = `LSM_MEMIO;
253 next_lsm_state = `LSM_SETUP;
255 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
259 if(next_regs == 16'b0) begin
260 next_lsm_state = `LSM_BASEWB;
263 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
267 next_lsm_state = `LSM_WBFLUSH;
268 $display("LDMSTM: Stage 3: Writing back");
272 next_lsm_state = `LSM_SETUP;
276 next_lsm_state = 4'bxxxx;
279 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
281 `DECODE_LDCSTC: if(!inbubble) begin
282 $display("WARNING: Unimplemented LDCSTC");
284 `DECODE_CDP: if (!inbubble) begin
289 /* XXX undefined instruction trap */
290 $display("WARNING: Possible CDP undefined instruction");
293 `DECODE_MRCMCR: if (!inbubble) begin
298 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
300 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
306 /* Coprocessor input. */
311 cp_write = 32'hxxxxxxxx;
313 `DECODE_CDP: if(!inbubble) begin
316 `DECODE_MRCMCR: if(!inbubble) begin
318 cp_rnw = insn[20] /* L */;
319 if (insn[20] == 0 /* store to coprocessor */)
325 /* Register output logic. */
328 next_write_reg = write_reg;
329 next_write_num = write_num;
330 next_write_data = write_data;
331 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
332 next_outcpsrup = cpsrup;
335 `DECODE_ALU_SWP: if (!inbubble) begin
336 next_write_reg = 1'bx;
337 next_write_num = 4'bxxxx;
338 next_write_data = 32'hxxxxxxxx;
341 next_write_reg = 1'b0;
343 next_write_reg = 1'b1;
344 next_write_num = insn[15:12];
345 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
350 `DECODE_ALU_MULT: begin end
351 `DECODE_ALU_HDATA_REG,
352 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
353 next_write_reg = 1'bx;
354 next_write_num = 4'bxxxx;
355 next_write_data = 32'hxxxxxxxx;
358 next_write_num = insn[15:12];
359 next_write_data = lsrh_rddata;
361 next_write_reg = 1'b1;
365 next_write_reg = 1'b1;
366 next_write_num = insn[19:16];
367 next_write_data = addr;
370 next_write_reg = 1'b0;
374 `DECODE_LDRSTR_UNDEFINED: begin end
375 `DECODE_LDRSTR: if(!inbubble) begin
376 next_write_reg = 1'bx;
377 next_write_num = 4'bxxxx;
378 next_write_data = 32'hxxxxxxxx;
381 next_write_reg = insn[20] /* L */;
382 next_write_num = insn[15:12];
383 if(insn[20] /* L */) begin
384 next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
388 next_write_reg = 1'b0;
390 next_write_reg = 1'b1;
391 next_write_num = insn[19:16];
392 next_write_data = addr;
395 next_write_reg = 1'b0;
399 `DECODE_LDMSTM: if(!inbubble) begin
400 next_write_reg = 1'bx;
401 next_write_num = 4'bxxxx;
402 next_write_data = 32'hxxxxxxxx;
405 next_write_reg = 1'b0;
408 next_write_reg = !rw_wait;
409 next_write_num = cur_reg;
410 next_write_data = rd_data;
412 next_write_reg = 1'b0;
415 next_write_reg = insn[21] /* writeback */;
416 next_write_num = insn[19:16];
417 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
418 if(cur_reg == 4'hF && insn[22]) begin
424 next_write_reg = 1'b0;
428 `DECODE_MRCMCR: if(!inbubble) begin
429 next_write_reg = 1'bx;
430 next_write_num = 4'bxxxx;
431 next_write_data = 32'hxxxxxxxx;
432 next_outcpsr = 32'hxxxxxxxx;
433 next_outcpsrup = 1'bx;
434 if (insn[20] == 1 /* load from coprocessor */)
435 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
436 next_write_reg = 1'b1;
437 next_write_num = insn[15:12];
438 next_write_data = cp_read;
440 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
447 /* Bus control logic. */
452 wr_data = 32'hxxxxxxxx;
453 offset = prev_offset;
455 raddr = 32'hxxxxxxxx;
456 busaddr = 32'hxxxxxxxx;
460 `DECODE_ALU_SWP: if(!inbubble) begin
461 busaddr = {op0[31:2], 2'b0};
462 data_size = insn[22] ? 3'b001 : 3'b100;
468 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
473 `DECODE_ALU_MULT: begin end
474 `DECODE_ALU_HDATA_REG,
475 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
476 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
477 raddr = insn[24] ? op0 : addr; /* pre/post increment */
479 /* rotate to correct position */
481 2'b01: begin /* unsigned half */
482 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
485 2'b10: begin /* signed byte */
486 wr_data = {4{op2[7:0]}};
489 2'b11: begin /* signed half */
490 wr_data = {2{op2[15:0]}};
494 wr_data = 32'hxxxxxxxx;
504 `LSRH_BASEWB: begin end
505 `LSRH_WBFLUSH: begin end
509 `DECODE_LDRSTR_UNDEFINED: begin end
510 `DECODE_LDRSTR: if(!inbubble) begin
511 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
512 raddr = insn[24] ? addr : op0; /* pre/post increment */
514 wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
515 data_size = insn[22] ? 3'b001 : 3'b100;
518 rd_req = insn[20] /* L */ || insn[22] /* B */;
519 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
524 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
525 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
526 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
527 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
530 `LSR_BASEWB: begin end
531 `LSR_WBFLUSH: begin end
535 `DECODE_LDMSTM: if (!inbubble) begin
543 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
544 offset = prev_offset + 6'h4;
545 offset_sel = insn[24] ? offset : prev_offset;
546 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
549 `LSM_BASEWB: begin end
550 `LSM_WBFLUSH: begin end
554 `DECODE_LDCSTC: begin end
555 `DECODE_CDP: begin end
556 `DECODE_MRCMCR: begin end
564 do_rd_data_latch = 0;
566 next_outbubble = inbubble;
569 offset = prev_offset;
570 lsrh_rddata = 32'hxxxxxxxx;
571 lsrh_rddata_s1 = 16'hxxxx;
572 lsrh_rddata_s2 = 8'hxx;
573 next_swp_oldval = swp_oldval;
576 /* XXX shit not given about endianness */
578 `DECODE_ALU_SWP: if(!inbubble) begin
579 next_outbubble = rw_wait;
583 next_swp_oldval = rd_data;
584 `SWP_WRITING: begin end
588 `DECODE_ALU_MULT: begin end
589 `DECODE_ALU_HDATA_REG,
590 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
591 next_outbubble = rw_wait;
593 /* rotate to correct position */
595 2'b01: begin /* unsigned half */
596 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
598 2'b10: begin /* signed byte */
599 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
600 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
601 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
603 2'b11: begin /* signed half */
604 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
607 lsrh_rddata = 32'hxxxxxxxx;
612 `LSRH_MEMIO: begin end
614 next_outbubble = 1'b0;
615 `LSRH_WBFLUSH: begin end
619 `DECODE_LDRSTR_UNDEFINED: begin end
620 `DECODE_LDRSTR: if(!inbubble) begin
621 next_outbubble = rw_wait;
622 /* rotate to correct position */
623 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
624 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
625 /* select byte or word */
626 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
629 if (insn[22] /* B */ && !insn[20] /* L */)
630 do_rd_data_latch = 1;
631 `LSR_STRB_WR: begin end
634 `LSR_WBFLUSH: begin end
638 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
639 `DECODE_LDMSTM: if(!inbubble) begin
640 next_outbubble = rw_wait;
643 // next_regs = insn[23] ? op1[15:0] : op1[0:15];
644 /** verilator can suck my dick */
645 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
646 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
650 16'b???????????????1: begin
652 next_regs = {regs[15:1], 1'b0};
654 16'b??????????????10: begin
656 next_regs = {regs[15:2], 2'b0};
658 16'b?????????????100: begin
660 next_regs = {regs[15:3], 3'b0};
662 16'b????????????1000: begin
664 next_regs = {regs[15:4], 4'b0};
666 16'b???????????10000: begin
668 next_regs = {regs[15:5], 5'b0};
670 16'b??????????100000: begin
672 next_regs = {regs[15:6], 6'b0};
674 16'b?????????1000000: begin
676 next_regs = {regs[15:7], 7'b0};
678 16'b????????10000000: begin
680 next_regs = {regs[15:8], 8'b0};
682 16'b???????100000000: begin
684 next_regs = {regs[15:9], 9'b0};
686 16'b??????1000000000: begin
688 next_regs = {regs[15:10], 10'b0};
690 16'b?????10000000000: begin
692 next_regs = {regs[15:11], 11'b0};
694 16'b????100000000000: begin
696 next_regs = {regs[15:12], 12'b0};
698 16'b???1000000000000: begin
700 next_regs = {regs[15:13], 13'b0};
702 16'b??10000000000000: begin
704 next_regs = {regs[15:14], 14'b0};
706 16'b?100000000000000: begin
708 next_regs = {regs[15], 15'b0};
710 16'b1000000000000000: begin
719 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
723 cur_reg = prev_reg; /* whoops, do this one again */
730 `LSM_WBFLUSH: begin end
734 `DECODE_LDCSTC: begin end
735 `DECODE_CDP: if(!inbubble) begin
740 `DECODE_MRCMCR: if(!inbubble) begin
748 if ((flush || delayedflush) && !outstall)
749 next_outbubble = 1'b1;