xst: Add synthesis files (part 1).
[firearm.git] / xst / sim / tb.v
1 `timescale 1 ns/1 ps
2
3 module tb();
4   reg clk = 0;
5   wire [8:0] odata;
6   
7   System system(.clk(clk), .rst(1'b0), .sys_odata(odata), .sys_idata(9'b0), .sys_tookdata(tookdata));
8   glbl glbl();
9   
10   initial begin
11     $monitor($stime,,"odata: %x = %c", odata, odata[7:0]);
12     while(1)
13       #30 clk <= ~clk;
14   end
15 endmodule
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