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xst: Add synthesis files (part 1).
[firearm.git]
/
xst
/
sim
/
tb.v
1
`timescale 1 ns/1 ps
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module tb();
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reg clk = 0;
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wire [8:0] odata;
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System system(.clk(clk), .rst(1'b0), .sys_odata(odata), .sys_idata(9'b0), .sys_tookdata(tookdata));
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glbl glbl();
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initial begin
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$monitor($stime,,"odata: %x = %c", odata, odata[7:0]);
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while(1)
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#30 clk <= ~clk;
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end
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endmodule
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