Memory: wire -> reg in some cases
[firearm.git] / Memory.v
1 `include "ARM_Constants.v"
2
3 module Memory(
4         input clk,
5         input Nrst,
6
7         input flush,
8
9         /* bus interface */
10         output reg [31:0] busaddr,
11         output reg rd_req,
12         output reg wr_req,
13         input rw_wait,
14         output reg [31:0] wr_data,
15         input [31:0] rd_data,
16         output reg [2:0] data_size,
17
18         /* regfile interface */
19         output reg [3:0] st_read,
20         input [31:0] st_data,
21         
22         /* Coprocessor interface */
23         output reg cp_req,
24         input cp_ack,
25         input cp_busy,
26         output reg cp_rnw,      /* 1 = read from CP, 0 = write to CP */
27         input [31:0] cp_read,
28         output reg [31:0] cp_write,
29         
30         /* stage inputs */
31         input inbubble,
32         input [31:0] pc,
33         input [31:0] insn,
34         input [31:0] op0,
35         input [31:0] op1,
36         input [31:0] op2,
37         input [31:0] spsr,
38         input [31:0] cpsr,
39         input write_reg,
40         input [3:0] write_num,
41         input [31:0] write_data,
42
43         /* outputs */
44         output reg outstall,
45         output reg outbubble,
46         output reg [31:0] outpc,
47         output reg [31:0] outinsn,
48         output reg out_write_reg = 1'b0,
49         output reg [3:0] out_write_num = 4'bxxxx,
50         output reg [31:0] out_write_data = 32'hxxxxxxxx,
51         output reg [31:0] outspsr = 32'hxxxxxxxx,
52         output reg [31:0] outcpsr = 32'hxxxxxxxx
53         );
54
55         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
56         reg [31:0] prevaddr;
57         reg [3:0] next_regsel, cur_reg, prev_reg;
58         reg next_writeback;
59
60         reg next_outbubble;     
61         reg next_write_reg;
62         reg [3:0] next_write_num;
63         reg [31:0] next_write_data;
64
65         reg [1:0] lsr_state = 2'b01, next_lsr_state;
66         reg [31:0] align_s1, align_s2, align_rddata;
67
68         reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
69         reg [31:0] lsrh_rddata;
70         reg [15:0] lsrh_rddata_s1;
71         reg [7:0] lsrh_rddata_s2;
72
73         reg [15:0] regs, next_regs;
74         reg [2:0] lsm_state = 3'b001, next_lsm_state;
75         reg [5:0] offset, prev_offset, offset_sel;
76
77         reg [31:0] swp_oldval, next_swp_oldval;
78         reg [1:0] swp_state = 2'b01, next_swp_state;
79
80         always @(posedge clk)
81         begin
82                 outpc <= pc;
83                 outinsn <= insn;
84                 outbubble <= next_outbubble;
85                 out_write_reg <= next_write_reg;
86                 out_write_num <= next_write_num;
87                 out_write_data <= next_write_data;
88                 regs <= next_regs;
89                 prev_reg <= cur_reg;
90                 prev_offset <= offset;
91                 prev_raddr <= raddr;
92                 outcpsr <= next_outcpsr;
93                 outspsr <= spsr;
94                 swp_state <= next_swp_state;
95                 lsm_state <= next_lsm_state;
96                 lsr_state <= next_lsr_state;
97                 lsrh_state <= next_lsrh_state;
98                 prevaddr <= addr;
99         end
100
101         always @(*)
102         begin
103                 addr = prevaddr;
104                 raddr = 32'hxxxxxxxx;
105                 rd_req = 1'b0;
106                 wr_req = 1'b0;
107                 wr_data = 32'hxxxxxxxx;
108                 busaddr = 32'hxxxxxxxx;
109                 data_size = 3'bxxx;
110                 outstall = 1'b0;
111                 next_write_reg = write_reg;
112                 next_write_num = write_num;
113                 next_write_data = write_data;
114                 next_outbubble = inbubble;
115                 next_regs = regs;
116                 cp_req = 1'b0;
117                 cp_rnw = 1'bx;
118                 cp_write = 32'hxxxxxxxx;
119                 offset = prev_offset;
120                 next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
121                 lsrh_rddata = 32'hxxxxxxxx;
122                 lsrh_rddata_s1 = 16'hxxxx;
123                 lsrh_rddata_s2 = 8'hxx;
124                 next_lsm_state = lsm_state;
125                 next_lsr_state = lsr_state;
126                 next_lsrh_state = lsrh_state;
127                 next_swp_oldval = swp_oldval;
128                 next_swp_state = swp_state;
129                 cur_reg = prev_reg;
130
131                 /* XXX shit not given about endianness */
132                 if (flush)
133                         next_outbubble = 1'b1;
134                 else casez(insn)
135                 `DECODE_ALU_SWP: if(!inbubble) begin
136                         outstall = rw_wait;
137                         next_outbubble = rw_wait;
138                         busaddr = {op0[31:2], 2'b0};
139                         data_size = insn[22] ? 3'b001 : 3'b100;
140                         case(swp_state)
141                         2'b01: begin
142                                 rd_req = 1'b1;
143                                 outstall = 1'b1;
144                                 if(!rw_wait) begin
145                                         next_swp_state = 2'b10;
146                                         next_swp_oldval = rd_data;
147                                 end
148                         end
149                         2'b10: begin
150                                 wr_req = 1'b1;
151                                 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
152                                 next_write_reg = 1'b1;
153                                 next_write_num = insn[15:12];
154                                 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
155                                 if(!rw_wait)
156                                         next_swp_state = 2'b01;
157                         end
158                         default: begin end
159                         endcase
160                 end
161                 `DECODE_ALU_HDATA_REG,
162                 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
163                         next_outbubble = rw_wait;
164                         outstall = rw_wait;
165                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
166                         raddr = insn[24] ? op0 : addr; /* pre/post increment */
167                         busaddr = raddr;
168                         /* rotate to correct position */
169                         case(insn[6:5])
170                         2'b00: begin end /* swp */
171                         2'b01: begin /* unsigned half */
172                                 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
173                                 data_size = 3'b010;
174                                 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
175                         end
176                         2'b10: begin /* signed byte */
177                                 wr_data = {4{op2[7:0]}};
178                                 data_size = 3'b001;
179                                 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
180                                 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
181                                 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
182                         end
183                         2'b11: begin /* signed half */
184                                 wr_data = {2{op2[15:0]}};
185                                 data_size = 3'b010;
186                                 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
187                         end
188                         endcase
189
190                         case(lsrh_state)
191                         2'b01: begin
192                                 rd_req = insn[20];
193                                 wr_req = ~insn[20];
194                                 next_write_num = insn[15:12];
195                                 next_write_data = lsrh_rddata;
196                                 if(insn[20]) begin
197                                         next_write_reg = 1'b1;
198                                 end
199                                 if(insn[21] | !insn[24]) begin
200                                         outstall = 1'b1;
201                                         if(!rw_wait)
202                                                 next_lsrh_state = 2'b10;
203                                 end
204                         end
205                         2'b10: begin
206                                 next_write_reg = 1'b1;
207                                 next_write_num = insn[19:16];
208                                 next_write_data = addr;
209                                 next_lsrh_state = 2'b10;
210                         end
211                         default: begin end
212                         endcase
213                 end
214                 `DECODE_LDRSTR_UNDEFINED: begin end
215                 `DECODE_LDRSTR: if(!inbubble) begin
216                         next_outbubble = rw_wait;
217                         outstall = rw_wait;
218                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
219                         raddr = insn[24] ? op0 : addr; /* pre/post increment */
220                         busaddr = raddr;
221                         /* rotate to correct position */
222                         align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
223                         align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
224                         /* select byte or word */
225                         align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
226                         wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
227                         data_size = insn[22] ? 3'b001 : 3'b100;
228                         case(lsr_state)
229                         2'b01: begin
230                                 rd_req = insn[20];
231                                 wr_req = ~insn[20];
232                                 next_write_reg = 1'b1;
233                                 next_write_num = insn[15:12];
234                                 if(insn[20]) begin
235                                         next_write_data = align_rddata;
236                                 end
237                                 if(insn[21] | !insn[24]) begin
238                                         outstall = 1'b1;
239                                         if(!rw_wait)
240                                                 next_lsr_state = 2'b10;
241                                 end
242                         end
243                         2'b10: begin
244                                 next_write_reg = 1'b1;
245                                 next_write_num = insn[19:16];
246                                 next_write_data = addr;
247                                 next_lsr_state = 2'b10;
248                         end
249                         default: begin end
250                         endcase
251                 end
252                 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
253                 `DECODE_LDMSTM: if(!inbubble) begin
254                         outstall = rw_wait;
255                         next_outbubble = rw_wait;
256                         data_size = 3'b100;
257                         case(lsm_state)
258                         3'b001: begin
259 //                              next_regs = insn[23] ? op1[15:0] : op1[0:15];
260                                 /** verilator can suck my dick */
261                                 next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
262                                                                     op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
263                                 offset = 6'b0;
264                                 outstall = 1'b1;
265                                 next_lsm_state = 3'b010;
266                         end
267                         3'b010: begin
268                                 rd_req = insn[20];
269                                 wr_req = ~insn[20];
270                                 casez(regs)
271                                 16'b???????????????1: begin
272                                         cur_reg = 4'h0;
273                                         next_regs = {regs[15:1], 1'b0};
274                                 end
275                                 16'b??????????????10: begin
276                                         cur_reg = 4'h1;
277                                         next_regs = {regs[15:2], 2'b0};
278                                 end
279                                 16'b?????????????100: begin
280                                         cur_reg = 4'h2;
281                                         next_regs = {regs[15:3], 3'b0};
282                                 end
283                                 16'b????????????1000: begin
284                                         cur_reg = 4'h3;
285                                         next_regs = {regs[15:4], 4'b0};
286                                 end
287                                 16'b???????????10000: begin
288                                         cur_reg = 4'h4;
289                                         next_regs = {regs[15:5], 5'b0};
290                                 end
291                                 16'b??????????100000: begin
292                                         cur_reg = 4'h5;
293                                         next_regs = {regs[15:6], 6'b0};
294                                 end
295                                 16'b?????????1000000: begin
296                                         cur_reg = 4'h6;
297                                         next_regs = {regs[15:7], 7'b0};
298                                 end
299                                 16'b????????10000000: begin
300                                         cur_reg = 4'h7;
301                                         next_regs = {regs[15:8], 8'b0};
302                                 end
303                                 16'b???????100000000: begin
304                                         cur_reg = 4'h8;
305                                         next_regs = {regs[15:9], 9'b0};
306                                 end
307                                 16'b??????1000000000: begin
308                                         cur_reg = 4'h9;
309                                         next_regs = {regs[15:10], 10'b0};
310                                 end
311                                 16'b?????10000000000: begin
312                                         cur_reg = 4'hA;
313                                         next_regs = {regs[15:11], 11'b0};
314                                 end
315                                 16'b????100000000000: begin
316                                         cur_reg = 4'hB;
317                                         next_regs = {regs[15:12], 12'b0};
318                                 end
319                                 16'b???1000000000000: begin
320                                         cur_reg = 4'hC;
321                                         next_regs = {regs[15:13], 13'b0};
322                                 end
323                                 16'b??10000000000000: begin
324                                         cur_reg = 4'hD;
325                                         next_regs = {regs[15:14], 14'b0};
326                                 end
327                                 16'b?100000000000000: begin
328                                         cur_reg = 4'hE;
329                                         next_regs = {regs[15], 15'b0};
330                                 end
331                                 16'b1000000000000000: begin
332                                         cur_reg = 4'hF;
333                                         next_regs = 16'b0;
334                                 end
335                                 default: begin
336                                         cur_reg = 4'hx;
337                                         next_regs = 16'b0;
338                                 end
339                                 endcase
340                                 cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
341                                 if(cur_reg == 4'hF && insn[22]) begin
342                                         next_outcpsr = spsr;
343                                 end
344
345                                 if(rw_wait) begin
346                                         next_regs = regs;
347                                         cur_reg = prev_reg;
348                                         raddr = prev_raddr;
349                                 end
350                                 else begin
351                                         offset = prev_offset + 6'h4;
352                                         offset_sel = insn[24] ? offset : prev_offset;
353                                         raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
354                                         if(insn[20]) begin
355                                                 next_write_reg = 1'b1;
356                                                 next_write_num = cur_reg;
357                                                 next_write_data = rd_data;
358                                         end
359                                 end
360
361                                 st_read = cur_reg;
362                                 wr_data = st_data;
363                                 busaddr = raddr;
364
365                                 outstall = 1'b1;
366
367                                 if(next_regs == 16'b0) begin
368                                         next_lsm_state = 3'b100;
369                                 end
370                         end
371                         3'b100: begin
372                                 next_write_reg = 1'b1;
373                                 next_write_num = insn[19:16];
374                                 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
375                                 next_lsm_state = 3'b001;
376                         end
377                         default: begin end
378                         endcase
379                 end
380                 `DECODE_LDCSTC: if(!inbubble) begin
381                         $display("WARNING: Unimplemented LDCSTC");
382                 end
383                 `DECODE_CDP: if(!inbubble) begin
384                         cp_req = 1;
385                         if (cp_busy) begin
386                                 outstall = 1;
387                                 next_outbubble = 1;
388                         end
389                         if (!cp_ack) begin
390                                 /* XXX undefined instruction trap */
391                                 $display("WARNING: Possible CDP undefined instruction");
392                         end
393                 end
394                 `DECODE_MRCMCR: if(!inbubble) begin
395                         cp_req = 1;
396                         cp_rnw = insn[20] /* L */;
397                         if (insn[20] == 0 /* store to coprocessor */)
398                                 cp_write = op0;
399                         else begin
400                                 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
401                                         next_write_reg = 1'b1;
402                                         next_write_num = insn[15:12];
403                                         next_write_data = cp_read;
404                                 end else
405                                         next_outcpsr = {cp_read[31:28], cpsr[27:0]};
406                         end
407                         if (cp_busy) begin
408                                 outstall = 1;
409                                 next_outbubble = 1;
410                         end
411                         if (!cp_ack) begin
412                                 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
413                         end
414                         $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
415                 end
416                 default: begin end
417                 endcase
418         end
419 endmodule
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