tests/Makefile: Add a target to pad binaries for Xilinx tools.
[firearm.git] / Memory.v
1 `include "ARM_Constants.v"
2
3 module Memory(
4         input clk,
5         input Nrst,
6
7         input flush,
8
9         /* bus interface */
10         output reg [31:0] busaddr,
11         output reg rd_req,
12         output reg wr_req,
13         input rw_wait,
14         output reg [31:0] wr_data,
15         input [31:0] rd_data,
16         output reg [2:0] data_size,
17
18         /* regfile interface */
19         output reg [3:0] st_read,
20         input [31:0] st_data,
21         
22         /* Coprocessor interface */
23         output reg cp_req,
24         input cp_ack,
25         input cp_busy,
26         output reg cp_rnw,      /* 1 = read from CP, 0 = write to CP */
27         input [31:0] cp_read,
28         output reg [31:0] cp_write,
29         
30         /* stage inputs */
31         input inbubble,
32         input [31:0] pc,
33         input [31:0] insn,
34         input [31:0] op0,
35         input [31:0] op1,
36         input [31:0] op2,
37         input [31:0] spsr,
38         input [31:0] cpsr,
39         input cpsrup,
40         input write_reg,
41         input [3:0] write_num,
42         input [31:0] write_data,
43
44         /* outputs */
45         output reg outstall,
46         output reg outbubble,
47         output reg [31:0] outpc,
48         output reg [31:0] outinsn,
49         output reg out_write_reg = 1'b0,
50         output reg [3:0] out_write_num = 4'bxxxx,
51         output reg [31:0] out_write_data = 32'hxxxxxxxx,
52         output reg [31:0] outspsr = 32'hxxxxxxxx,
53         output reg [31:0] outcpsr = 32'hxxxxxxxx,
54         output reg outcpsrup = 1'hx
55         );
56
57         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
58         reg next_outcpsrup;
59         reg [31:0] prevaddr;
60         reg [3:0] next_regsel, cur_reg, prev_reg;
61         reg next_writeback;
62
63         reg next_outbubble;     
64         reg next_write_reg;
65         reg [3:0] next_write_num;
66         reg [31:0] next_write_data;
67
68         reg [3:0] lsr_state = 4'b0001, next_lsr_state;
69         reg [31:0] align_s1, align_s2, align_rddata;
70
71         reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
72         reg [31:0] lsrh_rddata;
73         reg [15:0] lsrh_rddata_s1;
74         reg [7:0] lsrh_rddata_s2;
75
76         reg [15:0] regs, next_regs;
77         reg [3:0] lsm_state = 4'b0001, next_lsm_state;
78         reg [5:0] offset, prev_offset, offset_sel;
79
80         reg [31:0] swp_oldval, next_swp_oldval;
81         reg [1:0] swp_state = 2'b01, next_swp_state;
82         
83         reg do_rd_data_latch;
84         reg [31:0] rd_data_latch = 32'hxxxxxxxx;
85
86         always @(posedge clk)
87         begin
88                 outpc <= pc;
89                 outinsn <= insn;
90                 outbubble <= next_outbubble;
91                 out_write_reg <= next_write_reg;
92                 out_write_num <= next_write_num;
93                 out_write_data <= next_write_data;
94                 regs <= next_regs;
95                 prev_reg <= cur_reg;
96                 if (!rw_wait)
97                         prev_offset <= offset;
98                 prev_raddr <= raddr;
99                 outcpsr <= next_outcpsr;
100                 outspsr <= spsr;
101                 outcpsrup <= next_outcpsrup;
102                 swp_state <= next_swp_state;
103                 lsm_state <= next_lsm_state;
104                 lsr_state <= next_lsr_state;
105                 lsrh_state <= next_lsrh_state;
106                 if (do_rd_data_latch)
107                         rd_data_latch <= rd_data;
108                 prevaddr <= addr;
109         end
110         
111         reg delayedflush = 0;
112         always @(posedge clk)
113                 if (flush && outstall /* halp! I can't do it now, maybe later? */)
114                         delayedflush <= 1;
115                 else if (!outstall /* anything has been handled this time around */)
116                         delayedflush <= 0;
117
118         always @(*)
119         begin
120                 addr = prevaddr;
121                 raddr = 32'hxxxxxxxx;
122                 rd_req = 1'b0;
123                 wr_req = 1'b0;
124                 wr_data = 32'hxxxxxxxx;
125                 busaddr = 32'hxxxxxxxx;
126                 data_size = 3'bxxx;
127                 outstall = 1'b0;
128                 st_read = 4'hx;
129                 do_rd_data_latch = 0;
130                 next_write_reg = write_reg;
131                 next_write_num = write_num;
132                 next_write_data = write_data;
133                 next_outbubble = inbubble;
134                 next_regs = regs;
135                 cp_req = 1'b0;
136                 cp_rnw = 1'bx;
137                 cp_write = 32'hxxxxxxxx;
138                 offset = prev_offset;
139                 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
140                 next_outcpsrup = cpsrup;
141                 lsrh_rddata = 32'hxxxxxxxx;
142                 lsrh_rddata_s1 = 16'hxxxx;
143                 lsrh_rddata_s2 = 8'hxx;
144                 next_lsm_state = lsm_state;
145                 next_lsr_state = lsr_state;
146                 next_lsrh_state = lsrh_state;
147                 next_swp_oldval = swp_oldval;
148                 next_swp_state = swp_state;
149                 cur_reg = prev_reg;
150
151                 /* XXX shit not given about endianness */
152                 casez(insn)
153                 `DECODE_ALU_SWP: if(!inbubble) begin
154                         outstall = rw_wait;
155                         next_outbubble = rw_wait;
156                         busaddr = {op0[31:2], 2'b0};
157                         data_size = insn[22] ? 3'b001 : 3'b100;
158                         case(swp_state)
159                         2'b01: begin
160                                 rd_req = 1'b1;
161                                 outstall = 1'b1;
162                                 if(!rw_wait) begin
163                                         next_swp_state = 2'b10;
164                                         next_swp_oldval = rd_data;
165                                 end
166                                 $display("SWP: read stage");
167                         end
168                         2'b10: begin
169                                 wr_req = 1'b1;
170                                 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
171                                 next_write_reg = 1'b1;
172                                 next_write_num = insn[15:12];
173                                 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
174                                 if(!rw_wait)
175                                         next_swp_state = 2'b01;
176                                 $display("SWP: write stage");
177                         end
178                         default: begin end
179                         endcase
180                 end
181                 `DECODE_ALU_MULT: begin end
182                 `DECODE_ALU_HDATA_REG,
183                 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
184                         next_outbubble = rw_wait;
185                         outstall = rw_wait;
186                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
187                         raddr = insn[24] ? op0 : addr; /* pre/post increment */
188                         busaddr = raddr;
189                         /* rotate to correct position */
190                         case(insn[6:5])
191                         2'b00: begin end /* swp */
192                         2'b01: begin /* unsigned half */
193                                 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
194                                 data_size = 3'b010;
195                                 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
196                         end
197                         2'b10: begin /* signed byte */
198                                 wr_data = {4{op2[7:0]}};
199                                 data_size = 3'b001;
200                                 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
201                                 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
202                                 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
203                         end
204                         2'b11: begin /* signed half */
205                                 wr_data = {2{op2[15:0]}};
206                                 data_size = 3'b010;
207                                 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
208                         end
209                         endcase
210
211                         case(lsrh_state)
212                         3'b001: begin
213                                 rd_req = insn[20];
214                                 wr_req = ~insn[20];
215                                 next_write_num = insn[15:12];
216                                 next_write_data = lsrh_rddata;
217                                 if(insn[20]) begin
218                                         next_write_reg = 1'b1;
219                                 end
220                                 if(insn[21] | !insn[24]) begin
221                                         outstall = 1'b1;
222                                         if(!rw_wait)
223                                                 next_lsrh_state = 3'b010;
224                                 end
225                                 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
226                         end
227                         3'b010: begin
228                                 next_outbubble = 1'b0;
229                                 next_write_reg = 1'b1;
230                                 next_write_num = insn[19:16];
231                                 next_write_data = addr;
232                                 next_lsrh_state = 3'b100;
233                         end
234                         3'b100: begin
235                                 outstall = 0;
236                                 next_lsrh_state = 3'b001;
237                         end
238                         default: begin end
239                         endcase
240                         
241                         if ((lsrh_state == 3'b001) && flush) begin      /* Reject it. */
242                                 outstall = 1'b0;
243                                 next_lsrh_state = 3'b001;
244                         end
245                 end
246                 `DECODE_LDRSTR_UNDEFINED: begin end
247                 `DECODE_LDRSTR: if(!inbubble) begin
248                         next_outbubble = rw_wait;
249                         outstall = rw_wait;
250                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
251                         raddr = insn[24] ? addr : op0; /* pre/post increment */
252                         busaddr = raddr;
253                         /* rotate to correct position */
254                         align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
255                         align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
256                         /* select byte or word */
257                         align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
258                         wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
259                         data_size = insn[22] ? 3'b001 : 3'b100;
260                         case(lsr_state)
261                         4'b0001: begin
262                                 rd_req = insn[20] /* L */ || insn[22] /* B */;
263                                 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
264                                 next_write_reg = insn[20] /* L */;
265                                 next_write_num = insn[15:12];
266                                 if(insn[20] /* L */) begin
267                                         next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
268                                 end
269                                 if (insn[22] /* B */ && !insn[20] /* L */) begin
270                                         do_rd_data_latch = 1;
271                                         outstall = 1'b1;
272                                         if (!rw_wait)
273                                                 next_lsr_state = 4'b0010;       /* XXX: One-hot, my ass. */
274                                 end else if(insn[21] /* W */ | !insn[24] /* P */) begin
275                                         outstall = 1'b1;
276                                         if(!rw_wait)
277                                                 next_lsr_state = 4'b0100;
278                                 end
279                                 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
280                         end
281                         4'b0010: begin
282                                 $display("LDRSTR: Handling STRB");
283                                 outstall = 1;
284                                 rd_req = 0;
285                                 wr_req = 1;
286                                 next_write_reg = 0;
287                                 case (busaddr[1:0])
288                                 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
289                                 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
290                                 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
291                                 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
292                                 endcase
293                                 if(insn[21] /* W */ | !insn[24] /* P */) begin
294                                         if(!rw_wait)
295                                                 next_lsr_state = 4'b0100;
296                                 end else if (!rw_wait)
297                                         next_lsr_state = 4'b1000;
298                         end
299                         4'b0100: begin
300                                 outstall = 1;
301                                 rd_req = 0;
302                                 wr_req= 0;
303                                 next_outbubble = 0;
304                                 next_write_reg = 1'b1;
305                                 next_write_num = insn[19:16];
306                                 next_write_data = addr;
307                                 next_lsr_state = 4'b1000;
308                         end
309                         4'b1000: begin
310                                 rd_req = 0;
311                                 wr_req= 0;
312                                 outstall = 0;
313                                 next_lsr_state = 4'b0001;
314                         end
315                         default: begin end
316                         endcase
317                         
318                         if ((lsr_state == 4'b0001) && flush) begin      /* Reject it. */
319                                 outstall = 1'b0;
320                                 next_lsr_state = 4'b0001;
321                         end
322                 end
323                 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
324                 `DECODE_LDMSTM: if(!inbubble) begin
325                         outstall = rw_wait;
326                         next_outbubble = rw_wait;
327                         data_size = 3'b100;
328                         case(lsm_state)
329                         4'b0001: begin
330 //                              next_regs = insn[23] ? op1[15:0] : op1[0:15];
331                                 /** verilator can suck my dick */
332                                 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
333                                 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
334                                                                             op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
335                                 offset = 6'b0;
336                                 outstall = 1'b1;
337                                 next_lsm_state = 4'b0010;
338                         end
339                         4'b0010: begin
340                                 rd_req = insn[20];
341                                 wr_req = ~insn[20];
342                                 casez(regs)
343                                 16'b???????????????1: begin
344                                         cur_reg = 4'h0;
345                                         next_regs = {regs[15:1], 1'b0};
346                                 end
347                                 16'b??????????????10: begin
348                                         cur_reg = 4'h1;
349                                         next_regs = {regs[15:2], 2'b0};
350                                 end
351                                 16'b?????????????100: begin
352                                         cur_reg = 4'h2;
353                                         next_regs = {regs[15:3], 3'b0};
354                                 end
355                                 16'b????????????1000: begin
356                                         cur_reg = 4'h3;
357                                         next_regs = {regs[15:4], 4'b0};
358                                 end
359                                 16'b???????????10000: begin
360                                         cur_reg = 4'h4;
361                                         next_regs = {regs[15:5], 5'b0};
362                                 end
363                                 16'b??????????100000: begin
364                                         cur_reg = 4'h5;
365                                         next_regs = {regs[15:6], 6'b0};
366                                 end
367                                 16'b?????????1000000: begin
368                                         cur_reg = 4'h6;
369                                         next_regs = {regs[15:7], 7'b0};
370                                 end
371                                 16'b????????10000000: begin
372                                         cur_reg = 4'h7;
373                                         next_regs = {regs[15:8], 8'b0};
374                                 end
375                                 16'b???????100000000: begin
376                                         cur_reg = 4'h8;
377                                         next_regs = {regs[15:9], 9'b0};
378                                 end
379                                 16'b??????1000000000: begin
380                                         cur_reg = 4'h9;
381                                         next_regs = {regs[15:10], 10'b0};
382                                 end
383                                 16'b?????10000000000: begin
384                                         cur_reg = 4'hA;
385                                         next_regs = {regs[15:11], 11'b0};
386                                 end
387                                 16'b????100000000000: begin
388                                         cur_reg = 4'hB;
389                                         next_regs = {regs[15:12], 12'b0};
390                                 end
391                                 16'b???1000000000000: begin
392                                         cur_reg = 4'hC;
393                                         next_regs = {regs[15:13], 13'b0};
394                                 end
395                                 16'b??10000000000000: begin
396                                         cur_reg = 4'hD;
397                                         next_regs = {regs[15:14], 14'b0};
398                                 end
399                                 16'b?100000000000000: begin
400                                         cur_reg = 4'hE;
401                                         next_regs = {regs[15], 15'b0};
402                                 end
403                                 16'b1000000000000000: begin
404                                         cur_reg = 4'hF;
405                                         next_regs = 16'b0;
406                                 end
407                                 default: begin
408                                         cur_reg = 4'hx;
409                                         next_regs = 16'b0;
410                                 end
411                                 endcase
412                                 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
413                                 if(cur_reg == 4'hF && insn[22]) begin
414                                         next_outcpsr = spsr;
415                                         next_outcpsrup = 1;
416                                 end
417
418                                 offset = prev_offset + 6'h4;
419                                 offset_sel = insn[24] ? offset : prev_offset;
420                                 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
421                                 if(insn[20]) begin
422                                         next_write_reg = !rw_wait;
423                                         next_write_num = cur_reg;
424                                         next_write_data = rd_data;
425                                 end
426                                 if (rw_wait) begin
427                                         next_regs = regs;
428                                         cur_reg = prev_reg;     /* whoops, do this one again */
429                                 end
430
431                                 st_read = cur_reg;
432                                 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
433                                 busaddr = raddr;
434                                 
435                                 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
436
437                                 outstall = 1'b1;
438
439                                 if(next_regs == 16'b0) begin
440                                         next_lsm_state = 4'b0100;
441                                 end
442                         end
443                         4'b0100: begin
444                                 outstall = 1;
445                                 next_outbubble = 0;
446                                 next_write_reg = insn[21] /* writeback */;
447                                 next_write_num = insn[19:16];
448                                 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
449                                 next_lsm_state = 4'b1000;
450                                 $display("LDMSTM: Stage 3: Writing back");
451                         end
452                         4'b1000: begin
453                                 outstall = 0;
454                                 next_lsm_state = 4'b0001;
455                         end
456                         default: $stop;
457                         endcase
458                         if ((lsm_state == 4'b0001) && flush) begin      /* Reject it. */
459                                 outstall = 1'b0;
460                                 next_lsm_state = 4'b0001;
461                         end
462                         $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
463                 end
464                 `DECODE_LDCSTC: if(!inbubble) begin
465                         $display("WARNING: Unimplemented LDCSTC");
466                 end
467                 `DECODE_CDP: if(!inbubble) begin
468                         cp_req = 1;
469                         if (cp_busy) begin
470                                 outstall = 1;
471                                 next_outbubble = 1;
472                         end
473                         if (!cp_ack) begin
474                                 /* XXX undefined instruction trap */
475                                 $display("WARNING: Possible CDP undefined instruction");
476                         end
477                 end
478                 `DECODE_MRCMCR: if(!inbubble) begin
479                         cp_req = 1;
480                         cp_rnw = insn[20] /* L */;
481                         if (insn[20] == 0 /* store to coprocessor */)
482                                 cp_write = op0;
483                         else begin
484                                 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
485                                         next_write_reg = 1'b1;
486                                         next_write_num = insn[15:12];
487                                         next_write_data = cp_read;
488                                 end else begin
489                                         next_outcpsr = {cp_read[31:28], cpsr[27:0]};
490                                         next_outcpsrup = 1;
491                                 end
492                         end
493                         if (cp_busy) begin
494                                 outstall = 1;
495                                 next_outbubble = 1;
496                         end
497                         if (!cp_ack) begin
498                                 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
499                         end
500                         $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
501                 end
502                 default: begin end
503                 endcase
504                 
505                 if ((flush || delayedflush) && !outstall)
506                         next_outbubble = 1'b1;
507         end
508 endmodule
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