Memory.v

   1 `include "ARM_Constants.v"
   2
   3 module Memory(
   4         input clk,
   5         input Nrst,
   6
   7         /* bus interface */
   8         output reg [31:0] busaddr,
   9         output reg rd_req,
  10         output reg wr_req,
  11         input rw_wait,
  12         output reg [31:0] wr_data,
  13         input [31:0] rd_data,
  14
  15         /* regfile interface */
  16         output reg [3:0] st_read,
  17         input [31:0] st_data,
  18
  19         /* Coprocessor interface */
  20         output reg cp_req,
  21         input cp_ack,
  22         input cp_busy,
  23
  24         /* stage inputs */
  25         input inbubble,
  26         input [31:0] pc,
  27         input [31:0] insn,
  28         input [31:0] op0,
  29         input [31:0] op1,
  30         input [31:0] op2,
  31         input [31:0] spsr,
  32         input [31:0] cpsr,
  33         input write_reg,
  34         input [3:0] write_num,
  35         input [31:0] write_data,
  36
  37         /* outputs */
  38         output reg outstall,
  39         output reg outbubble,
  40         output reg [31:0] outpc,
  41         output reg [31:0] outinsn,
  42         output reg out_write_reg = 1'b0,
  43         output reg [3:0] out_write_num = 4'bxxxx,
  44         output reg [31:0] out_write_data = 32'hxxxxxxxx,
  45         output reg [31:0] out_spsr = 32'hxxxxxxxx,
  46         output reg [31:0] out_cpsr = 32'hxxxxxxxx
  47         );
  48
  49         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
  50         reg [3:0] next_regsel, cur_reg, prev_reg;
  51         reg next_writeback, next_notdone, next_inc_next;
  52         reg [31:0] align_s1, align_s2, align_rddata;
  53
  54         wire next_outbubble;
  55         wire next_write_reg;
  56         wire [3:0] next_write_num;
  57         wire [31:0] next_write_data;
  58
  59         reg [15:0] regs, next_regs;
  60         reg started = 1'b0, next_started;
  61         reg [5:0] offset, prev_offset, offset_sel;
  62
  63         reg notdone = 1'b0;
  64         reg inc_next = 1'b0;
  65
  66         always @(posedge clk)
  67         begin
  68                 outpc <= pc;
  69                 outinsn <= insn;
  70                 outbubble <= next_outbubble;
  71                 out_write_reg <= next_write_reg;
  72                 out_write_num <= next_write_num;
  73                 out_write_data <= next_write_data;
  74                 notdone <= next_notdone;
  75                 inc_next <= next_inc_next;
  76                 regs <= next_regs;
  77                 prev_reg <= cur_reg;
  78                 started <= next_started;
  79                 prev_offset <= offset;
  80                 prev_raddr <= raddr;
  81                 out_cpsr <= next_outcpsr;
  82                 out_spsr <= spsr;
  83         end
  84
  85         always @(*)
  86         begin
  87                 addr = 32'hxxxxxxxx;
  88                 raddr = 32'hxxxxxxxx;
  89                 rd_req = 1'b0;
  90                 wr_req = 1'b0;
  91                 wr_data = 32'hxxxxxxxx;
  92                 busaddr = 32'hxxxxxxxx;
  93                 outstall = 1'b0;
  94                 next_notdone = 1'b0;
  95                 next_write_reg = write_reg;
  96                 next_write_num = write_num;
  97                 next_write_data = write_data;
  98                 next_inc_next = 1'b0;
  99                 next_outbubble = inbubble;
 100                 outstall = 1'b0;
 101                 next_regs = 16'b0;
 102                 next_started = started;
 103                 cp_req = 1'b0;
 104                 offset = prev_offset;
 105                 next_outcpsr = started ? out_cpsr : cpsr;
 106
 107                 casez(insn)
 108                 `DECODE_LDRSTR_UNDEFINED: begin end
 109                 `DECODE_LDRSTR: begin
 110                         if (!inbubble) begin
 111                                 next_outbubble = rw_wait;
 112                                 outstall = rw_wait | notdone;
 113
 114                                 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
 115                                 raddr = insn[24] ? op0 : addr; /* pre/post increment */
 116                                 busaddr = {raddr[31:2], 2'b0};
 117                                 rd_req = insn[20];
 118                                 wr_req = ~insn[20];
 119
 120                                 /* rotate to correct position */
 121                                 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
 122                                 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
 123                                 /* select byte or word */
 124                                 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
 125
 126                                 if(!insn[20]) begin
 127                                         wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
 128                                 end
 129                                 else if(!inc_next) begin
 130                                         next_write_reg = 1'b1;
 131                                         next_write_num = insn[15:12];
 132                                         next_write_data = align_rddata;
 133                                         next_inc_next = 1'b1;
 134                                 end
 135                                 else if(insn[21]) begin
 136                                         next_write_reg = 1'b1;
 137                                         next_write_num = insn[19:16];
 138                                         next_write_data = addr;
 139                                 end
 140                                 next_notdone = rw_wait & insn[20] & insn[21];
 141                         end
 142                 end
 143                 `DECODE_LDMSTM: begin
 144                         rd_req = insn[20];
 145                         wr_req = ~insn[20];
 146                         if(!started) begin
 147 //                              next_regs = insn[23] ? op1[15:0] : op1[0:15];
 148                                 /** verilator can suck my dick */
 149                                 next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
 150                                                                     op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
 151                                 offset = 6'b0;
 152                                 next_started = 1'b1;
 153                         end
 154                         else if(inc_next) begin
 155                                 if(insn[21]) begin
 156                                         next_write_reg = 1'b1;
 157                                         next_write_num = insn[19:16];
 158                                         next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
 159                                 end
 160                                 next_started = 1'b0;
 161                         end
 162                         else if(rw_wait) begin
 163                                 next_regs = regs;
 164                                 cur_reg = prev_reg;
 165                                 raddr = prev_raddr;
 166                         end
 167                         else begin
 168                                 casez(regs)
 169                                 16'b???????????????1: begin
 170                                         cur_reg = 4'h0;
 171                                         next_regs = {regs[15:1], 1'b0};
 172                                 end
 173                                 16'b??????????????10: begin
 174                                         cur_reg = 4'h1;
 175                                         next_regs = {regs[15:2], 2'b0};
 176                                 end
 177                                 16'b?????????????100: begin
 178                                         cur_reg = 4'h2;
 179                                         next_regs = {regs[15:3], 3'b0};
 180                                 end
 181                                 16'b????????????1000: begin
 182                                         cur_reg = 4'h3;
 183                                         next_regs = {regs[15:4], 4'b0};
 184                                 end
 185                                 16'b???????????10000: begin
 186                                         cur_reg = 4'h4;
 187                                         next_regs = {regs[15:5], 5'b0};
 188                                 end
 189                                 16'b??????????100000: begin
 190                                         cur_reg = 4'h5;
 191                                         next_regs = {regs[15:6], 6'b0};
 192                                 end
 193                                 16'b?????????1000000: begin
 194                                         cur_reg = 4'h6;
 195                                         next_regs = {regs[15:7], 7'b0};
 196                                 end
 197                                 16'b????????10000000: begin
 198                                         cur_reg = 4'h7;
 199                                         next_regs = {regs[15:8], 8'b0};
 200                                 end
 201                                 16'b???????100000000: begin
 202                                         cur_reg = 4'h8;
 203                                         next_regs = {regs[15:9], 9'b0};
 204                                 end
 205                                 16'b??????1000000000: begin
 206                                         cur_reg = 4'h9;
 207                                         next_regs = {regs[15:10], 10'b0};
 208                                 end
 209                                 16'b?????10000000000: begin
 210                                         cur_reg = 4'hA;
 211                                         next_regs = {regs[15:11], 11'b0};
 212                                 end
 213                                 16'b????100000000000: begin
 214                                         cur_reg = 4'hB;
 215                                         next_regs = {regs[15:12], 12'b0};
 216                                 end
 217                                 16'b???1000000000000: begin
 218                                         cur_reg = 4'hC;
 219                                         next_regs = {regs[15:13], 13'b0};
 220                                 end
 221                                 16'b??10000000000000: begin
 222                                         cur_reg = 4'hD;
 223                                         next_regs = {regs[15:14], 14'b0};
 224                                 end
 225                                 16'b?100000000000000: begin
 226                                         cur_reg = 4'hE;
 227                                         next_regs = {regs[15], 15'b0};
 228                                 end
 229                                 16'b1000000000000000: begin
 230                                         cur_reg = 4'hF;
 231                                         next_regs = 16'b0;
 232                                 end
 233                                 default: begin
 234                                         cur_reg = 4'hx;
 235                                         next_regs = 16'b0;
 236                                 end
 237                                 endcase
 238                                 cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
 239                                 if(cur_reg == 4'hF && insn[22]) begin
 240                                         next_outcpsr = spsr;
 241                                 end
 242                                 offset = prev_offset + 6'h4;
 243                                 offset_sel = insn[24] ? offset : prev_offset;
 244                                 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
 245
 246                                 if(insn[20]) begin
 247                                         next_write_reg = 1'b1;
 248                                         next_write_num = cur_reg;
 249                                         next_write_data = rd_data;
 250                                 end
 251
 252                                 st_read = cur_reg;
 253                                 wr_data = st_data;
 254
 255                                 next_inc_next = next_regs == 16'b0;
 256                                 next_notdone = ~next_inc_next | rw_wait;
 257                                 busaddr = {raddr[31:2], 2'b0};
 258                         end
 259                 end
 260                 default: begin end
 261                 endcase
 262         end
 263 endmodule