xst/iic_init.v

   1 `timescale 1 ns / 100 ps
   2 module iic_init( Clk,                          //I
   3                  Reset_n,                      //I
   4                  Pixel_clk_greater_than_65Mhz, //I
   5                  SDA,                          //IO
   6                  SCL,                          //IO
   7                  Done                          //O
   8                  );
   9
  10 input Clk;
  11 input Reset_n;
  12 input Pixel_clk_greater_than_65Mhz;
  13 inout SDA;
  14 inout SCL;
  15 output Done;
  16
  17 parameter CLK_RATE_MHZ = 200,
  18           SCK_PERIOD_US = 30,
  19           TRANSITION_CYCLE = (CLK_RATE_MHZ * SCK_PERIOD_US) / 2,
  20           TRANSITION_CYCLE_MSB = 11;
  21
  22
  23 localparam    IDLE = 3'd0,
  24               INIT = 3'd1,
  25               START = 3'd2,
  26               CLK_FALL = 3'd3,
  27               SETUP = 3'd4,
  28               CLK_RISE = 3'd5,
  29               WAIT = 3'd6,
  30               START_BIT = 1'b1,
  31               SLAVE_ADDR= 7'b1110110,
  32               ACK = 1'b1,
  33               WRITE = 1'b0,
  34               REG_ADDR0 = 8'h49,
  35               REG_ADDR1 = 8'h21,
  36               REG_ADDR2 = 8'h33,
  37               REG_ADDR3 = 8'h34,
  38               REG_ADDR4 = 8'h36,
  39               DATA0 = 8'hC0,
  40               DATA1 = 8'h09,
  41               DATA2a = 8'h06,
  42               DATA3a = 8'h26,
  43               DATA4a = 8'hA0,
  44               DATA2b = 8'h08,
  45               DATA3b = 8'h16,
  46               DATA4b = 8'h60,
  47               STOP_BIT=1'b0,
  48               SDA_BUFFER_MSB=27;
  49
  50 reg SDA_out;
  51 reg SCL_out;
  52 reg [TRANSITION_CYCLE_MSB:0] cycle_count;
  53 reg [2:0] c_state;
  54 reg [2:0] n_state;
  55 reg Done;
  56 reg [2:0] write_count;
  57 reg [31:0] bit_count;
  58 reg [SDA_BUFFER_MSB:0] SDA_BUFFER;
  59 wire transition;
  60
  61 always @ (posedge Clk) begin
  62     if (~Reset_n||c_state==IDLE ) begin
  63         SDA_out <= 1'b1;
  64         SCL_out <=1'b1;
  65     end
  66     else if (c_state==INIT && transition) begin
  67         SDA_out <=1'b0;
  68     end
  69     else if (c_state==SETUP) begin
  70         SDA_out <=SDA_BUFFER[SDA_BUFFER_MSB];
  71     end
  72     else if (c_state==CLK_RISE && cycle_count==TRANSITION_CYCLE/2 && bit_count==SDA_BUFFER_MSB) begin
  73         SDA_out <= 1'b1;
  74     end
  75     else if (c_state==CLK_FALL) begin
  76         SCL_out <=1'b0;
  77     end
  78
  79     else if (c_state==CLK_RISE) begin
  80         SCL_out <=1'b1;
  81     end
  82 end
  83
  84 //OBUFT_LVCMOS33 sda0(.O(SDA), .I(1'b0), .T(SDA_out));
  85 //OBUFT_LVCMOS33 scl0(.O(SCL), .I(1'b0), .T(SCL_out));
  86 assign SDA = SDA_out;
  87 assign SCL = SCL_out;
  88
  89 always @ (posedge Clk) begin
  90     //reset or end condition
  91     if(~Reset_n) begin
  92        SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR0,ACK,DATA0,ACK,STOP_BIT};
  93        cycle_count<=0;
  94
  95     end
  96     //setup sda for sck rise
  97     else if ( c_state==SETUP && cycle_count==TRANSITION_CYCLE)begin
  98        SDA_BUFFER <= {SDA_BUFFER[SDA_BUFFER_MSB-1:0],1'b0};
  99        cycle_count<=0;
 100     end
 101     //reset count at end of state
 102     else if ( cycle_count==TRANSITION_CYCLE)
 103        cycle_count<=0;
 104     //reset sda_buffer
 105     else if (c_state==WAIT && Pixel_clk_greater_than_65Mhz   )begin
 106        case(write_count)
 107          0:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR1,ACK,DATA1,ACK,STOP_BIT};
 108          1:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR2,ACK,DATA2a,ACK,STOP_BIT};
 109          2:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR3,ACK,DATA3a,ACK,STOP_BIT};
 110          3:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR4,ACK,DATA4a,ACK,STOP_BIT};
 111          default: SDA_BUFFER <=28'dx;
 112        endcase
 113        cycle_count<=cycle_count+1;
 114
 115     end
 116     else if (c_state==WAIT &&   ~Pixel_clk_greater_than_65Mhz )begin
 117        case(write_count)
 118          0:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR1,ACK,DATA1,ACK,STOP_BIT};
 119          1:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR2,ACK,DATA2b,ACK,STOP_BIT};
 120          2:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR3,ACK,DATA3b,ACK,STOP_BIT};
 121          3:SDA_BUFFER <= {SLAVE_ADDR,WRITE,ACK,REG_ADDR4,ACK,DATA4b,ACK,STOP_BIT};
 122          default: SDA_BUFFER <=28'dx;
 123        endcase
 124        cycle_count<=cycle_count+1;
 125     end
 126     else
 127        cycle_count<=cycle_count+1;
 128 end
 129
 130 always @ (posedge Clk) begin
 131  if(~Reset_n)
 132    write_count<=3'd0;
 133  else if (c_state==WAIT && cycle_count==TRANSITION_CYCLE)
 134    write_count<=write_count+1;
 135 end
 136
 137
 138 always @ (posedge Clk) begin
 139     if(~Reset_n)
 140       Done<=1'b0;
 141     else if (c_state==IDLE)
 142       Done<=1'b1;
 143 end
 144
 145
 146
 147
 148 always @ (posedge Clk) begin
 149     if(~Reset_n||(c_state==WAIT))
 150        bit_count<=0;
 151     else if ( c_state==CLK_RISE && cycle_count==TRANSITION_CYCLE)
 152        bit_count<=bit_count+1;
 153 end
 154
 155
 156
 157 always @ (posedge Clk) begin
 158     if(~Reset_n)
 159        c_state<=INIT;
 160     else
 161        c_state<=n_state;
 162 end
 163
 164
 165
 166 assign transition = (cycle_count==TRANSITION_CYCLE);
 167
 168 //Next state
 169 always @ (*) begin
 170    case(c_state)
 171        IDLE: begin
 172           if(~Reset_n) n_state = INIT;
 173           else n_state = IDLE;
 174        end
 175        INIT: begin
 176           if (transition) n_state = START;
 177           else n_state = INIT;
 178        end
 179        START: begin
 180           if(~Reset_n) n_state = INIT;
 181           else if( transition) n_state = CLK_FALL;
 182           else n_state = START;
 183        end
 184        CLK_FALL: begin
 185           if(~Reset_n) n_state = INIT;
 186           else if( transition) n_state = SETUP;
 187           else n_state = CLK_FALL;
 188        end
 189        SETUP: begin
 190           if(~Reset_n) n_state = INIT;
 191           else if( transition) n_state = CLK_RISE;
 192           else n_state = SETUP;
 193        end
 194        CLK_RISE: begin
 195           if(~Reset_n)
 196              n_state = INIT;
 197           else if( transition && bit_count==SDA_BUFFER_MSB)
 198              n_state = WAIT;
 199           else if (transition )
 200              n_state = CLK_FALL;
 201           else n_state = CLK_RISE;
 202        end
 203        WAIT: begin
 204           if(~Reset_n|(transition && write_count!=3'd4))
 205              n_state = INIT;
 206           else if (transition )
 207              n_state = IDLE;
 208           else n_state = WAIT;
 209        end
 210        default: n_state = IDLE;
 211
 212    endcase
 213 end
 214
 215
 216
 217
 218
 219 endmodule