DCache/ICache: reg i -> integer i
[firearm.git] / RegFile.v
1 module RegFile(
2         input clk,
3         input [3:0] read_0,
4         output reg [31:0] rdata_0,
5         input [3:0] read_1,
6         output reg [31:0] rdata_1,
7         input [3:0] read_2,
8         output reg [31:0] rdata_2,
9         input [3:0] read_3,
10         output reg [31:0] rdata_3,
11         output reg [31:0] spsr,
12         input write,
13         input [3:0] write_reg,
14         input [31:0] write_data
15         );
16         
17         reg [31:0] regfile [0:15];
18         
19         initial begin
20                 regfile[4'h0] = 32'h00000005;
21                 regfile[4'h1] = 32'h00000050;
22                 regfile[4'h2] = 32'h00000500;
23                 regfile[4'h3] = 32'h00005000;
24                 regfile[4'h4] = 32'h00050000;
25                 regfile[4'h5] = 32'h00500000;
26                 regfile[4'h6] = 32'h05000000;
27                 regfile[4'h7] = 32'h50000000;
28                 regfile[4'h8] = 32'hA0000000;
29                 regfile[4'h9] = 32'h0A000000;
30                 regfile[4'hA] = 32'h00A00000;
31                 regfile[4'hB] = 32'h000A0000;
32                 regfile[4'hC] = 32'h0000A000;
33                 regfile[4'hD] = 32'h00000A00;
34                 regfile[4'hE] = 32'h000000A0;
35                 regfile[4'hF] = 32'h00000000;   /* Start off claiming we are in user mode. */
36         end
37         
38         always @(*)
39         begin
40                 if ((read_0 == write_reg) && write)
41                         rdata_0 = write_data;
42                 else
43                         rdata_0 = regfile[read_0];
44                 
45                 if ((read_1 == write_reg) && write)
46                         rdata_1 = write_data;
47                 else
48                         rdata_1 = regfile[read_1];
49                 
50                 if ((read_2 == write_reg) && write)
51                         rdata_2 = write_data;
52                 else
53                         rdata_2 = regfile[read_2];
54
55                 if ((read_3 == write_reg) && write)
56                         rdata_3 = write_data;
57                 else
58                         rdata_3 = regfile[read_3];
59                 
60                 spsr = regfile[4'hF];
61         end
62         
63         always @(posedge clk)
64                 if (write)
65                         regfile[write_reg] <= write_data;
66 endmodule
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