Memory.v

   1 `include "ARM_Constants.v"
   2
   3 module Memory(
   4         input clk,
   5         input Nrst,
   6
   7         /* bus interface */
   8         output reg [31:0] busaddr,
   9         output reg rd_req,
  10         output reg wr_req,
  11         input rw_wait,
  12         output reg [31:0] wr_data,
  13         input [31:0] rd_data,
  14
  15         /* regfile interface */
  16         output reg [3:0] st_read,
  17         input [31:0] st_data,
  18
  19         /* Coprocessor interface */
  20         output reg cp_req,
  21         input cp_ack,
  22         input cp_busy,
  23         output cp_rnw,  /* 1 = read from CP, 0 = write to CP */
  24         input [31:0] cp_read,
  25         output reg [31:0] cp_write,
  26
  27         /* stage inputs */
  28         input inbubble,
  29         input [31:0] pc,
  30         input [31:0] insn,
  31         input [31:0] op0,
  32         input [31:0] op1,
  33         input [31:0] op2,
  34         input [31:0] spsr,
  35         input [31:0] cpsr,
  36         input write_reg,
  37         input [3:0] write_num,
  38         input [31:0] write_data,
  39
  40         /* outputs */
  41         output reg outstall,
  42         output reg outbubble,
  43         output reg [31:0] outpc,
  44         output reg [31:0] outinsn,
  45         output reg out_write_reg = 1'b0,
  46         output reg [3:0] out_write_num = 4'bxxxx,
  47         output reg [31:0] out_write_data = 32'hxxxxxxxx,
  48         output reg [31:0] out_spsr = 32'hxxxxxxxx,
  49         output reg [31:0] out_cpsr = 32'hxxxxxxxx
  50         );
  51
  52         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
  53         reg [3:0] next_regsel, cur_reg, prev_reg;
  54         reg next_writeback, next_notdone, next_inc_next;
  55         reg [31:0] align_s1, align_s2, align_rddata;
  56
  57         wire next_outbubble;
  58         wire next_write_reg;
  59         wire [3:0] next_write_num;
  60         wire [31:0] next_write_data;
  61
  62         reg [15:0] regs, next_regs;
  63         reg started = 1'b0, next_started;
  64         reg [5:0] offset, prev_offset, offset_sel;
  65
  66         reg notdone = 1'b0;
  67         reg inc_next = 1'b0;
  68
  69         always @(posedge clk)
  70         begin
  71                 outpc <= pc;
  72                 outinsn <= insn;
  73                 outbubble <= next_outbubble;
  74                 out_write_reg <= next_write_reg;
  75                 out_write_num <= next_write_num;
  76                 out_write_data <= next_write_data;
  77                 notdone <= next_notdone;
  78                 inc_next <= next_inc_next;
  79                 regs <= next_regs;
  80                 prev_reg <= cur_reg;
  81                 started <= next_started;
  82                 prev_offset <= offset;
  83                 prev_raddr <= raddr;
  84                 out_cpsr <= next_outcpsr;
  85                 out_spsr <= spsr;
  86         end
  87
  88         always @(*)
  89         begin
  90                 addr = 32'hxxxxxxxx;
  91                 raddr = 32'hxxxxxxxx;
  92                 rd_req = 1'b0;
  93                 wr_req = 1'b0;
  94                 wr_data = 32'hxxxxxxxx;
  95                 busaddr = 32'hxxxxxxxx;
  96                 outstall = 1'b0;
  97                 next_notdone = 1'b0;
  98                 next_write_reg = write_reg;
  99                 next_write_num = write_num;
 100                 next_write_data = write_data;
 101                 next_inc_next = 1'b0;
 102                 next_outbubble = inbubble;
 103                 outstall = 1'b0;
 104                 next_regs = 16'b0;
 105                 next_started = started;
 106                 cp_req = 1'b0;
 107                 cp_rnw = 1'bx;
 108                 cp_write = 32'hxxxxxxxx;
 109                 offset = prev_offset;
 110                 next_outcpsr = started ? out_cpsr : cpsr;
 111
 112                 casez(insn)
 113                 `DECODE_LDRSTR_UNDEFINED: begin end
 114                 `DECODE_LDRSTR: begin
 115                         if (!inbubble) begin
 116                                 next_outbubble = rw_wait;
 117                                 outstall = rw_wait | notdone;
 118
 119                                 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
 120                                 raddr = insn[24] ? op0 : addr; /* pre/post increment */
 121                                 busaddr = {raddr[31:2], 2'b0};
 122                                 rd_req = insn[20];
 123                                 wr_req = ~insn[20];
 124
 125                                 /* rotate to correct position */
 126                                 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
 127                                 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
 128                                 /* select byte or word */
 129                                 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
 130
 131                                 if(!insn[20]) begin
 132                                         wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
 133                                 end
 134                                 else if(!inc_next) begin
 135                                         next_write_reg = 1'b1;
 136                                         next_write_num = insn[15:12];
 137                                         next_write_data = align_rddata;
 138                                         next_inc_next = 1'b1;
 139                                 end
 140                                 else if(insn[21]) begin
 141                                         next_write_reg = 1'b1;
 142                                         next_write_num = insn[19:16];
 143                                         next_write_data = addr;
 144                                 end
 145                                 next_notdone = rw_wait & insn[20] & insn[21];
 146                         end
 147                 end
 148                 `DECODE_LDMSTM: begin
 149                         rd_req = insn[20];
 150                         wr_req = ~insn[20];
 151                         if(!started) begin
 152 //                              next_regs = insn[23] ? op1[15:0] : op1[0:15];
 153                                 /** verilator can suck my dick */
 154                                 next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
 155                                                                     op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
 156                                 offset = 6'b0;
 157                                 next_started = 1'b1;
 158                         end
 159                         else if(inc_next) begin
 160                                 if(insn[21]) begin
 161                                         next_write_reg = 1'b1;
 162                                         next_write_num = insn[19:16];
 163                                         next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
 164                                 end
 165                                 next_started = 1'b0;
 166                         end
 167                         else if(rw_wait) begin
 168                                 next_regs = regs;
 169                                 cur_reg = prev_reg;
 170                                 raddr = prev_raddr;
 171                         end
 172                         else begin
 173                                 casez(regs)
 174                                 16'b???????????????1: begin
 175                                         cur_reg = 4'h0;
 176                                         next_regs = {regs[15:1], 1'b0};
 177                                 end
 178                                 16'b??????????????10: begin
 179                                         cur_reg = 4'h1;
 180                                         next_regs = {regs[15:2], 2'b0};
 181                                 end
 182                                 16'b?????????????100: begin
 183                                         cur_reg = 4'h2;
 184                                         next_regs = {regs[15:3], 3'b0};
 185                                 end
 186                                 16'b????????????1000: begin
 187                                         cur_reg = 4'h3;
 188                                         next_regs = {regs[15:4], 4'b0};
 189                                 end
 190                                 16'b???????????10000: begin
 191                                         cur_reg = 4'h4;
 192                                         next_regs = {regs[15:5], 5'b0};
 193                                 end
 194                                 16'b??????????100000: begin
 195                                         cur_reg = 4'h5;
 196                                         next_regs = {regs[15:6], 6'b0};
 197                                 end
 198                                 16'b?????????1000000: begin
 199                                         cur_reg = 4'h6;
 200                                         next_regs = {regs[15:7], 7'b0};
 201                                 end
 202                                 16'b????????10000000: begin
 203                                         cur_reg = 4'h7;
 204                                         next_regs = {regs[15:8], 8'b0};
 205                                 end
 206                                 16'b???????100000000: begin
 207                                         cur_reg = 4'h8;
 208                                         next_regs = {regs[15:9], 9'b0};
 209                                 end
 210                                 16'b??????1000000000: begin
 211                                         cur_reg = 4'h9;
 212                                         next_regs = {regs[15:10], 10'b0};
 213                                 end
 214                                 16'b?????10000000000: begin
 215                                         cur_reg = 4'hA;
 216                                         next_regs = {regs[15:11], 11'b0};
 217                                 end
 218                                 16'b????100000000000: begin
 219                                         cur_reg = 4'hB;
 220                                         next_regs = {regs[15:12], 12'b0};
 221                                 end
 222                                 16'b???1000000000000: begin
 223                                         cur_reg = 4'hC;
 224                                         next_regs = {regs[15:13], 13'b0};
 225                                 end
 226                                 16'b??10000000000000: begin
 227                                         cur_reg = 4'hD;
 228                                         next_regs = {regs[15:14], 14'b0};
 229                                 end
 230                                 16'b?100000000000000: begin
 231                                         cur_reg = 4'hE;
 232                                         next_regs = {regs[15], 15'b0};
 233                                 end
 234                                 16'b1000000000000000: begin
 235                                         cur_reg = 4'hF;
 236                                         next_regs = 16'b0;
 237                                 end
 238                                 default: begin
 239                                         cur_reg = 4'hx;
 240                                         next_regs = 16'b0;
 241                                 end
 242                                 endcase
 243                                 cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
 244                                 if(cur_reg == 4'hF && insn[22]) begin
 245                                         next_outcpsr = spsr;
 246                                 end
 247                                 offset = prev_offset + 6'h4;
 248                                 offset_sel = insn[24] ? offset : prev_offset;
 249                                 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
 250
 251                                 if(insn[20]) begin
 252                                         next_write_reg = 1'b1;
 253                                         next_write_num = cur_reg;
 254                                         next_write_data = rd_data;
 255                                 end
 256
 257                                 st_read = cur_reg;
 258                                 wr_data = st_data;
 259
 260                                 next_inc_next = next_regs == 16'b0;
 261                                 next_notdone = ~next_inc_next | rw_wait;
 262                                 busaddr = {raddr[31:2], 2'b0};
 263                         end
 264                 end
 265                 `DECODE_LDCSTC: begin
 266                         $display("WARNING: Unimplemented LDCSTC");
 267                 end
 268                 `DECODE_CDP: begin
 269                         cp_req = 1;
 270                         if (cp_busy) begin
 271                                 outstall = 1;
 272                                 next_outbubble = 1;
 273                         end
 274                         if (!cp_ack) begin
 275                                 /* XXX undefined instruction trap */
 276                                 $display("WARNING: Possible CDP undefined instruction");
 277                         end
 278                 end
 279                 `DECODE_MRCMCR: begin
 280                         cp_req = 1;
 281                         cp_rnw = insn[20] /* L */;
 282                         if (insn[20] == 0 /* store to coprocessor */)
 283                                 cp_write = op0;
 284                         else begin
 285                                 next_write_reg = 1'b1;
 286                                 next_write_num = insn[15:12];
 287                                 next_write_data = cp_read;
 288                         end
 289                         if (cp_busy) begin
 290                                 outstall = 1;
 291                                 next_outbubble = 1;
 292                         end
 293                         if (!cp_ack) begin
 294                                 $display("WARNING: Possible MRCMCR undefined instruction");
 295                         end
 296                 end
 297                 default: begin end
 298                 endcase
 299         end
 300 endmodule