memory wea
[firearm.git] / Memory.v
1 `include "ARM_Constants.v"
2
3 module Memory(
4         input clk,
5         input Nrst,
6
7         /* bus interface */
8         output reg [31:0] busaddr,
9         output reg rd_req,
10         output reg wr_req,
11         input rw_wait,
12         output reg [31:0] wr_data,
13         input [31:0] rd_data,
14         output reg [2:0] data_size;
15
16         /* regfile interface */
17         output reg [3:0] st_read,
18         input [31:0] st_data,
19         
20         /* Coprocessor interface */
21         output reg cp_req,
22         input cp_ack,
23         input cp_busy,
24         output cp_rnw,  /* 1 = read from CP, 0 = write to CP */
25         input [31:0] cp_read,
26         output reg [31:0] cp_write,
27         
28         /* stage inputs */
29         input inbubble,
30         input [31:0] pc,
31         input [31:0] insn,
32         input [31:0] op0,
33         input [31:0] op1,
34         input [31:0] op2,
35         input [31:0] spsr,
36         input [31:0] cpsr,
37         input write_reg,
38         input [3:0] write_num,
39         input [31:0] write_data,
40
41         /* outputs */
42         output reg outstall,
43         output reg outbubble,
44         output reg [31:0] outpc,
45         output reg [31:0] outinsn,
46         output reg out_write_reg = 1'b0,
47         output reg [3:0] out_write_num = 4'bxxxx,
48         output reg [31:0] out_write_data = 32'hxxxxxxxx,
49         output reg [31:0] out_spsr = 32'hxxxxxxxx,
50         output reg [31:0] out_cpsr = 32'hxxxxxxxx
51         );
52
53         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
54         reg [31:0] prevaddr;
55         reg [3:0] next_regsel, cur_reg, prev_reg;
56         reg next_writeback;
57
58         wire next_outbubble;    
59         wire next_write_reg;
60         wire [3:0] next_write_num;
61         wire [31:0] next_write_data;
62
63         reg [1:0] lsr_state = 2'b01, next_lsr_state;
64         reg [31:0] align_s1, align_s2, align_rddata;
65
66         reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
67         reg [31:0] lsrh_rddata;
68         reg [15:0] lsrh_rddata_s1;
69         reg [7:0] lsrh_rddata_s2;
70
71         reg [15:0] regs, next_regs;
72         reg [2:0] lsm_state = 3'b001, next_lsm_state;
73         reg [5:0] offset, prev_offset, offset_sel;
74
75         reg [31:0] swp_oldval, next_swp_oldval;
76         reg [1:0] swp_state = 2'b01, next_swp_state;
77
78         always @(posedge clk)
79         begin
80                 outpc <= pc;
81                 outinsn <= insn;
82                 outbubble <= next_outbubble;
83                 out_write_reg <= next_write_reg;
84                 out_write_num <= next_write_num;
85                 out_write_data <= next_write_data;
86                 regs <= next_regs;
87                 prev_reg <= cur_reg;
88                 prev_offset <= offset;
89                 prev_raddr <= raddr;
90                 out_cpsr <= next_outcpsr;
91                 out_spsr <= spsr;
92                 swp_state <= next_swp_state;
93                 lsm_state <= next_lsm_state;
94                 lsr_state <= next_lsr_state;
95                 lsrh_state <= next_lsrh_state;
96                 prevaddr <= addr;
97         end
98
99         always @(*)
100         begin
101                 addr = prevaddr;
102                 raddr = 32'hxxxxxxxx;
103                 rd_req = 1'b0;
104                 wr_req = 1'b0;
105                 wr_data = 32'hxxxxxxxx;
106                 busaddr = 32'hxxxxxxxx;
107                 data_size = 3'bxxx;
108                 outstall = 1'b0;
109                 next_write_reg = write_reg;
110                 next_write_num = write_num;
111                 next_write_data = write_data;
112                 next_outbubble = inbubble;
113                 next_regs = regs;
114                 cp_req = 1'b0;
115                 cp_rnw = 1'bx;
116                 cp_write = 32'hxxxxxxxx;
117                 offset = prev_offset;
118                 next_outcpsr = lsm_state == 3'b010 ? out_cpsr : cpsr;
119                 lsrh_rddata = 32'hxxxxxxxx;
120                 lsrh_rddata_s1 = 32'hxxxxxxxx;
121                 lsrh_rddata_s2 = 32'hxxxxxxxx;
122                 next_lsm_state = lsm_state;
123                 next_lsr_state = lsr_state;
124                 next_lsrh_state = lsrh_state;
125                 next_swp_oldval = swp_oldval;
126                 next_swp_state = swp_state;
127                 cur_reg = prev_reg;
128
129                 /* XXX shit not given about endianness */
130                 casez(insn)
131                 `DECODE_ALU_SWP: if(!inbubble) begin
132                         outstall = rw_wait;
133                         next_outbubble = rw_wait;
134                         busaddr = {op0[31:2], 2'b0};
135                         data_size = insn[22] ? 3'b001 : 3'b100;
136                         case(swp_state)
137                         2'b01: begin
138                                 rd_req = 1'b1;
139                                 outstall = 1'b1;
140                                 if(!rw_wait) begin
141                                         next_swp_state = 2'b10;
142                                         next_swp_oldval = rd_data;
143                                 end
144                         end
145                         2'b10: begin
146                                 wr_req = 1'b1;
147                                 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
148                                 next_write_reg = 1'b1;
149                                 next_write_num = insn[15:12];
150                                 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
151                                 if(!rw_wait)
152                                         next_swp_state = 2'b01;
153                         end
154                         default: begin end
155                         endcase
156                 end
157                 `DECODE_ALU_HDATA_REG,
158                 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
159                         next_outbubble = rw_wait;
160                         outstall = rw_wait;
161                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
162                         raddr = insn[24] ? op0 : addr; /* pre/post increment */
163                         busaddr = raddr;
164                         /* rotate to correct position */
165                         case(insn[6:5])
166                         2'b00: begin end /* swp */
167                         2'b01: begin /* unsigned half */
168                                 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
169                                 data_size = 3'b010;
170                                 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
171                         end
172                         2'b10: begin /* signed byte */
173                                 wr_data = {4{op2[7:0]}};
174                                 data_size = 3'b001;
175                                 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
176                                 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
177                                 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
178                         end
179                         2'b11: begin /* signed half */
180                                 wr_data = {2{op2[15:0]}};
181                                 data_size = 3'b010;
182                                 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
183                         end
184                         endcase
185
186                         case(lsrh_state)
187                         2'b01: begin
188                                 rd_req = insn[20];
189                                 wr_req = ~insn[20];
190                                 next_write_num = insn[15:12];
191                                 next_write_data = lsrh_rddata;
192                                 if(insn[20]) begin
193                                         next_write_reg = 1'b1;
194                                 end
195                                 if(insn[21] | !insn[24]) begin
196                                         outstall = 1'b1;
197                                         if(!rw_wait)
198                                                 next_lsrh_state = 2'b10;
199                                 end
200                         end
201                         2'b10: begin
202                                 next_write_reg = 1'b1;
203                                 next_write_num = insn[19:16];
204                                 next_write_data = addr;
205                                 next_lsrh_state = 2'b10;
206                         end
207                         default: begin end
208                         endcase
209                 end
210                 `DECODE_LDRSTR_UNDEFINED: begin end
211                 `DECODE_LDRSTR: if(!inbubble) begin
212                         next_outbubble = rw_wait;
213                         outstall = rw_wait;
214                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
215                         raddr = insn[24] ? op0 : addr; /* pre/post increment */
216                         busaddr = raddr;
217                         /* rotate to correct position */
218                         align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
219                         align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
220                         /* select byte or word */
221                         align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
222                         wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
223                         data_size = insn[22] ? 3'b001 : 3'b100;
224                         case(lsr_state)
225                         2'b01: begin
226                                 rd_req = insn[20];
227                                 wr_req = ~insn[20];
228                                 next_write_reg = 1'b1;
229                                 next_write_num = insn[15:12];
230                                 if(insn[20]) begin
231                                         next_write_data = align_rddata;
232                                 end
233                                 if(insn[21] | !insn[24]) begin
234                                         outstall = 1'b1;
235                                         if(!rw_wait)
236                                                 next_lsr_state = 2'b10;
237                                 end
238                         end
239                         2'b10: begin
240                                 next_write_reg = 1'b1;
241                                 next_write_num = insn[19:16];
242                                 next_write_data = addr;
243                                 next_lsr_state = 2'b10;
244                         end
245                         default: begin end
246                         endcase
247                 end
248                 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
249                 `DECODE_LDMSTM: if(!inbubble) begin
250                         outstall = rw_wait;
251                         next_outbubble = rw_wait;
252                         data_size = 3'b100;
253                         case(lsm_state)
254                         3'b001: begin
255 //                              next_regs = insn[23] ? op1[15:0] : op1[0:15];
256                                 /** verilator can suck my dick */
257                                 next_regs = insn[23] ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
258                                                                     op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
259                                 offset = 6'b0;
260                                 outstall = 1'b1;
261                                 next_lsm_state = 3'b010;
262                         end
263                         3'b010: begin
264                                 rd_req = insn[20];
265                                 wr_req = ~insn[20];
266                                 casez(regs)
267                                 16'b???????????????1: begin
268                                         cur_reg = 4'h0;
269                                         next_regs = {regs[15:1], 1'b0};
270                                 end
271                                 16'b??????????????10: begin
272                                         cur_reg = 4'h1;
273                                         next_regs = {regs[15:2], 2'b0};
274                                 end
275                                 16'b?????????????100: begin
276                                         cur_reg = 4'h2;
277                                         next_regs = {regs[15:3], 3'b0};
278                                 end
279                                 16'b????????????1000: begin
280                                         cur_reg = 4'h3;
281                                         next_regs = {regs[15:4], 4'b0};
282                                 end
283                                 16'b???????????10000: begin
284                                         cur_reg = 4'h4;
285                                         next_regs = {regs[15:5], 5'b0};
286                                 end
287                                 16'b??????????100000: begin
288                                         cur_reg = 4'h5;
289                                         next_regs = {regs[15:6], 6'b0};
290                                 end
291                                 16'b?????????1000000: begin
292                                         cur_reg = 4'h6;
293                                         next_regs = {regs[15:7], 7'b0};
294                                 end
295                                 16'b????????10000000: begin
296                                         cur_reg = 4'h7;
297                                         next_regs = {regs[15:8], 8'b0};
298                                 end
299                                 16'b???????100000000: begin
300                                         cur_reg = 4'h8;
301                                         next_regs = {regs[15:9], 9'b0};
302                                 end
303                                 16'b??????1000000000: begin
304                                         cur_reg = 4'h9;
305                                         next_regs = {regs[15:10], 10'b0};
306                                 end
307                                 16'b?????10000000000: begin
308                                         cur_reg = 4'hA;
309                                         next_regs = {regs[15:11], 11'b0};
310                                 end
311                                 16'b????100000000000: begin
312                                         cur_reg = 4'hB;
313                                         next_regs = {regs[15:12], 12'b0};
314                                 end
315                                 16'b???1000000000000: begin
316                                         cur_reg = 4'hC;
317                                         next_regs = {regs[15:13], 13'b0};
318                                 end
319                                 16'b??10000000000000: begin
320                                         cur_reg = 4'hD;
321                                         next_regs = {regs[15:14], 14'b0};
322                                 end
323                                 16'b?100000000000000: begin
324                                         cur_reg = 4'hE;
325                                         next_regs = {regs[15], 15'b0};
326                                 end
327                                 16'b1000000000000000: begin
328                                         cur_reg = 4'hF;
329                                         next_regs = 16'b0;
330                                 end
331                                 default: begin
332                                         cur_reg = 4'hx;
333                                         next_regs = 16'b0;
334                                 end
335                                 endcase
336                                 cur_reg = insn[23] ? 4'hF - cur_reg : cur_reg;
337                                 if(cur_reg == 4'hF && insn[22]) begin
338                                         next_outcpsr = spsr;
339                                 end
340
341                                 if(rw_wait) begin
342                                         next_regs = regs;
343                                         cur_reg = prev_reg;
344                                         raddr = prev_raddr;
345                                 end
346                                 else begin
347                                         offset = prev_offset + 6'h4;
348                                         offset_sel = insn[24] ? offset : prev_offset;
349                                         raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
350                                         if(insn[20]) begin
351                                                 next_write_reg = 1'b1;
352                                                 next_write_num = cur_reg;
353                                                 next_write_data = rd_data;
354                                         end
355                                 end
356
357                                 st_read = cur_reg;
358                                 wr_data = st_data;
359                                 busaddr = raddr;
360
361                                 outstall = 1'b1;
362
363                                 if(next_regs == 16'b0) begin
364                                         next_lsm_state = 3'b100;
365                                 end
366                         end
367                         3'b100: begin
368                                 next_write_reg = 1'b1;
369                                 next_write_num = insn[19:16];
370                                 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
371                                 next_lsm_state = 3'b001;
372                         end
373                         default: begin end
374                         endcase
375                 end
376                 `DECODE_LDCSTC: if(!inbubble) begin
377                         $display("WARNING: Unimplemented LDCSTC");
378                 end
379                 `DECODE_CDP: if(!inbubble) begin
380                         cp_req = 1;
381                         if (cp_busy) begin
382                                 outstall = 1;
383                                 next_outbubble = 1;
384                         end
385                         if (!cp_ack) begin
386                                 /* XXX undefined instruction trap */
387                                 $display("WARNING: Possible CDP undefined instruction");
388                         end
389                 end
390                 `DECODE_MRCMCR: if(!inbubble) begin
391                         cp_req = 1;
392                         cp_rnw = insn[20] /* L */;
393                         if (insn[20] == 0 /* store to coprocessor */)
394                                 cp_write = op0;
395                         else begin
396                                 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
397                                         next_write_reg = 1'b1;
398                                         next_write_num = insn[15:12];
399                                         next_write_data = cp_read;
400                                 end else
401                                         next_outcpsr = {cp_read[31:28], cpsr[27:0]};
402                         end
403                         if (cp_busy) begin
404                                 outstall = 1;
405                                 next_outbubble = 1;
406                         end
407                         if (!cp_ack) begin
408                                 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
409                         end
410                         $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
411                 end
412                 default: begin end
413                 endcase
414         end
415 endmodule
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