2bab914d38470a31dd3a9de3cfe1e433c90166c2
[firearm.git] / Memory.v
1 `include "ARM_Constants.v"
2
3 module Memory(
4         input clk,
5         input Nrst,
6
7         input flush,
8
9         /* bus interface */
10         output reg [31:0] busaddr,
11         output reg rd_req,
12         output reg wr_req,
13         input rw_wait,
14         output reg [31:0] wr_data,
15         input [31:0] rd_data,
16         output reg [2:0] data_size,
17
18         /* regfile interface */
19         output reg [3:0] st_read,
20         input [31:0] st_data,
21         
22         /* Coprocessor interface */
23         output reg cp_req,
24         input cp_ack,
25         input cp_busy,
26         output reg cp_rnw,      /* 1 = read from CP, 0 = write to CP */
27         input [31:0] cp_read,
28         output reg [31:0] cp_write,
29         
30         /* stage inputs */
31         input inbubble,
32         input [31:0] pc,
33         input [31:0] insn,
34         input [31:0] op0,
35         input [31:0] op1,
36         input [31:0] op2,
37         input [31:0] spsr,
38         input [31:0] cpsr,
39         input write_reg,
40         input [3:0] write_num,
41         input [31:0] write_data,
42
43         /* outputs */
44         output reg outstall,
45         output reg outbubble,
46         output reg [31:0] outpc,
47         output reg [31:0] outinsn,
48         output reg out_write_reg = 1'b0,
49         output reg [3:0] out_write_num = 4'bxxxx,
50         output reg [31:0] out_write_data = 32'hxxxxxxxx,
51         output reg [31:0] outspsr = 32'hxxxxxxxx,
52         output reg [31:0] outcpsr = 32'hxxxxxxxx
53         );
54
55         reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
56         reg [31:0] prevaddr;
57         reg [3:0] next_regsel, cur_reg, prev_reg;
58         reg next_writeback;
59
60         reg next_outbubble;     
61         reg next_write_reg;
62         reg [3:0] next_write_num;
63         reg [31:0] next_write_data;
64
65         reg [1:0] lsr_state = 2'b01, next_lsr_state;
66         reg [31:0] align_s1, align_s2, align_rddata;
67
68         reg [1:0] lsrh_state = 2'b01, next_lsrh_state;
69         reg [31:0] lsrh_rddata;
70         reg [15:0] lsrh_rddata_s1;
71         reg [7:0] lsrh_rddata_s2;
72
73         reg [15:0] regs, next_regs;
74         reg [2:0] lsm_state = 3'b001, next_lsm_state;
75         reg [5:0] offset, prev_offset, offset_sel;
76
77         reg [31:0] swp_oldval, next_swp_oldval;
78         reg [1:0] swp_state = 2'b01, next_swp_state;
79
80         always @(posedge clk)
81         begin
82                 outpc <= pc;
83                 outinsn <= insn;
84                 outbubble <= next_outbubble;
85                 out_write_reg <= next_write_reg;
86                 out_write_num <= next_write_num;
87                 out_write_data <= next_write_data;
88                 regs <= next_regs;
89                 prev_reg <= cur_reg;
90                 prev_offset <= offset;
91                 prev_raddr <= raddr;
92                 outcpsr <= next_outcpsr;
93                 outspsr <= spsr;
94                 swp_state <= next_swp_state;
95                 lsm_state <= next_lsm_state;
96                 lsr_state <= next_lsr_state;
97                 lsrh_state <= next_lsrh_state;
98                 prevaddr <= addr;
99         end
100         
101         reg delayedflush = 0;
102         always @(posedge clk)
103                 if (flush && outstall /* halp! I can't do it now, maybe later? */)
104                         delayedflush <= 1;
105                 else if (!outstall /* anything has been handled this time around */)
106                         delayedflush <= 0;
107
108         always @(*)
109         begin
110                 addr = prevaddr;
111                 raddr = 32'hxxxxxxxx;
112                 rd_req = 1'b0;
113                 wr_req = 1'b0;
114                 wr_data = 32'hxxxxxxxx;
115                 busaddr = 32'hxxxxxxxx;
116                 data_size = 3'bxxx;
117                 outstall = 1'b0;
118                 next_write_reg = write_reg;
119                 next_write_num = write_num;
120                 next_write_data = write_data;
121                 next_outbubble = inbubble;
122                 next_regs = regs;
123                 cp_req = 1'b0;
124                 cp_rnw = 1'bx;
125                 cp_write = 32'hxxxxxxxx;
126                 offset = prev_offset;
127                 next_outcpsr = lsm_state == 3'b010 ? outcpsr : cpsr;
128                 lsrh_rddata = 32'hxxxxxxxx;
129                 lsrh_rddata_s1 = 16'hxxxx;
130                 lsrh_rddata_s2 = 8'hxx;
131                 next_lsm_state = lsm_state;
132                 next_lsr_state = lsr_state;
133                 next_lsrh_state = lsrh_state;
134                 next_swp_oldval = swp_oldval;
135                 next_swp_state = swp_state;
136                 cur_reg = prev_reg;
137
138                 /* XXX shit not given about endianness */
139                 casez(insn)
140                 `DECODE_ALU_SWP: if(!inbubble) begin
141                         outstall = rw_wait;
142                         next_outbubble = rw_wait;
143                         busaddr = {op0[31:2], 2'b0};
144                         data_size = insn[22] ? 3'b001 : 3'b100;
145                         case(swp_state)
146                         2'b01: begin
147                                 rd_req = 1'b1;
148                                 outstall = 1'b1;
149                                 if(!rw_wait) begin
150                                         next_swp_state = 2'b10;
151                                         next_swp_oldval = rd_data;
152                                 end
153                         end
154                         2'b10: begin
155                                 wr_req = 1'b1;
156                                 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
157                                 next_write_reg = 1'b1;
158                                 next_write_num = insn[15:12];
159                                 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
160                                 if(!rw_wait)
161                                         next_swp_state = 2'b01;
162                         end
163                         default: begin end
164                         endcase
165                 end
166                 `DECODE_ALU_HDATA_REG,
167                 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
168                         next_outbubble = rw_wait;
169                         outstall = rw_wait;
170                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
171                         raddr = insn[24] ? op0 : addr; /* pre/post increment */
172                         busaddr = raddr;
173                         /* rotate to correct position */
174                         case(insn[6:5])
175                         2'b00: begin end /* swp */
176                         2'b01: begin /* unsigned half */
177                                 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
178                                 data_size = 3'b010;
179                                 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
180                         end
181                         2'b10: begin /* signed byte */
182                                 wr_data = {4{op2[7:0]}};
183                                 data_size = 3'b001;
184                                 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
185                                 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
186                                 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
187                         end
188                         2'b11: begin /* signed half */
189                                 wr_data = {2{op2[15:0]}};
190                                 data_size = 3'b010;
191                                 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
192                         end
193                         endcase
194
195                         case(lsrh_state)
196                         2'b01: begin
197                                 rd_req = insn[20];
198                                 wr_req = ~insn[20];
199                                 next_write_num = insn[15:12];
200                                 next_write_data = lsrh_rddata;
201                                 if(insn[20]) begin
202                                         next_write_reg = 1'b1;
203                                 end
204                                 if(insn[21] | !insn[24]) begin
205                                         outstall = 1'b1;
206                                         if(!rw_wait)
207                                                 next_lsrh_state = 2'b10;
208                                 end
209                         end
210                         2'b10: begin
211                                 next_write_reg = 1'b1;
212                                 next_write_num = insn[19:16];
213                                 next_write_data = addr;
214                                 next_lsrh_state = 2'b10;
215                         end
216                         default: begin end
217                         endcase
218                 end
219                 `DECODE_LDRSTR_UNDEFINED: begin end
220                 `DECODE_LDRSTR: if(!inbubble) begin
221                         next_outbubble = rw_wait;
222                         outstall = rw_wait;
223                         addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
224                         raddr = insn[24] ? addr : op0; /* pre/post increment */
225                         busaddr = raddr;
226                         /* rotate to correct position */
227                         align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
228                         align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
229                         /* select byte or word */
230                         align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
231                         wr_data = insn[22] ? {4{op2[7:0]}} : op2; /* XXX need to actually store just a byte */
232                         data_size = insn[22] ? 3'b001 : 3'b100;
233                         case(lsr_state)
234                         2'b01: begin
235                                 rd_req = insn[20];
236                                 wr_req = ~insn[20];
237                                 next_write_reg = 1'b1;
238                                 next_write_num = insn[15:12];
239                                 if(insn[20]) begin
240                                         next_write_data = align_rddata;
241                                 end
242                                 if(insn[21] | !insn[24]) begin
243                                         outstall = 1'b1;
244                                         if(!rw_wait)
245                                                 next_lsr_state = 2'b10;
246                                 end
247                                 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
248                         end
249                         2'b10: begin
250                                 next_write_reg = 1'b1;
251                                 next_write_num = insn[19:16];
252                                 next_write_data = addr;
253                                 next_lsr_state = 2'b01;
254                         end
255                         default: begin end
256                         endcase
257                 end
258                 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
259                 `DECODE_LDMSTM: if(!inbubble) begin
260                         outstall = rw_wait;
261                         next_outbubble = rw_wait;
262                         data_size = 3'b100;
263                         case(lsm_state)
264                         3'b001: begin
265 //                              next_regs = insn[23] ? op1[15:0] : op1[0:15];
266                                 /** verilator can suck my dick */
267                                 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
268                                 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
269                                                                             op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
270                                 offset = 6'b0;
271                                 outstall = 1'b1;
272                                 next_lsm_state = 3'b010;
273                         end
274                         3'b010: begin
275                                 rd_req = insn[20];
276                                 wr_req = ~insn[20];
277                                 casez(regs)
278                                 16'b???????????????1: begin
279                                         cur_reg = 4'h0;
280                                         next_regs = {regs[15:1], 1'b0};
281                                 end
282                                 16'b??????????????10: begin
283                                         cur_reg = 4'h1;
284                                         next_regs = {regs[15:2], 2'b0};
285                                 end
286                                 16'b?????????????100: begin
287                                         cur_reg = 4'h2;
288                                         next_regs = {regs[15:3], 3'b0};
289                                 end
290                                 16'b????????????1000: begin
291                                         cur_reg = 4'h3;
292                                         next_regs = {regs[15:4], 4'b0};
293                                 end
294                                 16'b???????????10000: begin
295                                         cur_reg = 4'h4;
296                                         next_regs = {regs[15:5], 5'b0};
297                                 end
298                                 16'b??????????100000: begin
299                                         cur_reg = 4'h5;
300                                         next_regs = {regs[15:6], 6'b0};
301                                 end
302                                 16'b?????????1000000: begin
303                                         cur_reg = 4'h6;
304                                         next_regs = {regs[15:7], 7'b0};
305                                 end
306                                 16'b????????10000000: begin
307                                         cur_reg = 4'h7;
308                                         next_regs = {regs[15:8], 8'b0};
309                                 end
310                                 16'b???????100000000: begin
311                                         cur_reg = 4'h8;
312                                         next_regs = {regs[15:9], 9'b0};
313                                 end
314                                 16'b??????1000000000: begin
315                                         cur_reg = 4'h9;
316                                         next_regs = {regs[15:10], 10'b0};
317                                 end
318                                 16'b?????10000000000: begin
319                                         cur_reg = 4'hA;
320                                         next_regs = {regs[15:11], 11'b0};
321                                 end
322                                 16'b????100000000000: begin
323                                         cur_reg = 4'hB;
324                                         next_regs = {regs[15:12], 12'b0};
325                                 end
326                                 16'b???1000000000000: begin
327                                         cur_reg = 4'hC;
328                                         next_regs = {regs[15:13], 13'b0};
329                                 end
330                                 16'b??10000000000000: begin
331                                         cur_reg = 4'hD;
332                                         next_regs = {regs[15:14], 14'b0};
333                                 end
334                                 16'b?100000000000000: begin
335                                         cur_reg = 4'hE;
336                                         next_regs = {regs[15], 15'b0};
337                                 end
338                                 16'b1000000000000000: begin
339                                         cur_reg = 4'hF;
340                                         next_regs = 16'b0;
341                                 end
342                                 default: begin
343                                         cur_reg = 4'hx;
344                                         next_regs = 16'b0;
345                                 end
346                                 endcase
347                                 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
348                                 if(cur_reg == 4'hF && insn[22]) begin
349                                         next_outcpsr = spsr;
350                                 end
351
352                                 if (rw_wait)
353                                         offset = prev_offset;   /* whoops, do this one again */
354                                 else
355                                         offset = prev_offset + 6'h4;
356                                 offset_sel = insn[24] ? offset : prev_offset;
357                                 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
358                                 if(insn[20]) begin
359                                         next_write_reg = !rw_wait;
360                                         next_write_num = cur_reg;
361                                         next_write_data = rd_data;
362                                 end
363                                 if (rw_wait) begin
364                                         next_regs = regs;
365                                         cur_reg = prev_reg;     /* whoops, do this one again */
366                                 end
367
368                                 st_read = cur_reg;
369                                 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
370                                 busaddr = raddr;
371                                 
372                                 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
373
374                                 outstall = 1'b1;
375
376                                 if(next_regs == 16'b0) begin
377                                         next_lsm_state = 3'b100;
378                                 end
379                         end
380                         3'b100: begin
381                                 next_write_reg = insn[21] /* writeback */;
382                                 next_write_num = insn[19:16];
383                                 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
384                                 next_lsm_state = 3'b001;
385                                 $display("LDMSTM: Stage 3: Writing back");
386                         end
387                         default: $stop;
388                         endcase
389                         $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
390                 end
391                 `DECODE_LDCSTC: if(!inbubble) begin
392                         $display("WARNING: Unimplemented LDCSTC");
393                 end
394                 `DECODE_CDP: if(!inbubble) begin
395                         cp_req = 1;
396                         if (cp_busy) begin
397                                 outstall = 1;
398                                 next_outbubble = 1;
399                         end
400                         if (!cp_ack) begin
401                                 /* XXX undefined instruction trap */
402                                 $display("WARNING: Possible CDP undefined instruction");
403                         end
404                 end
405                 `DECODE_MRCMCR: if(!inbubble) begin
406                         cp_req = 1;
407                         cp_rnw = insn[20] /* L */;
408                         if (insn[20] == 0 /* store to coprocessor */)
409                                 cp_write = op0;
410                         else begin
411                                 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
412                                         next_write_reg = 1'b1;
413                                         next_write_num = insn[15:12];
414                                         next_write_data = cp_read;
415                                 end else
416                                         next_outcpsr = {cp_read[31:28], cpsr[27:0]};
417                         end
418                         if (cp_busy) begin
419                                 outstall = 1;
420                                 next_outbubble = 1;
421                         end
422                         if (!cp_ack) begin
423                                 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
424                         end
425                         $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
426                 end
427                 default: begin end
428                 endcase
429                 
430                 if ((flush || delayedflush) && !outstall)
431                         next_outbubble = 1'b1;
432         end
433 endmodule
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