Issue.v

   1 `include "ARM_Constants.v"
   2
   3 module Issue(
   4         input clk,
   5         input Nrst,
   6
   7         input stall,    /* pipeline control */
   8         input flush,
   9
  10         input inbubble, /* stage inputs */
  11         input [31:0] insn,
  12         input [31:0] inpc,
  13         input [31:0] cpsr,
  14
  15         output reg outbubble,   /* stage outputs */
  16         output reg [31:0] outpc
  17         /* other */
  18         );
  19
  20         always @(posedge clk)
  21         begin
  22                 outbubble <= inbubble;
  23                 outpc <= inpc;
  24         end
  25
  26 `ifdef COPY_PASTA_FODDER
  27         /* from page 2 of ARM7TDMIvE2.pdf */
  28         casex (insn)
  29         32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
  30 //      32'b????00001???????????????1001????:   /* Multiply long */
  31         32'b????00010?001111????000000000000:   /* MRS (Transfer PSR to register) */
  32         32'b????00010?101001111100000000????:   /* MSR (Transfer register to PSR) */
  33         32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
  34         32'b????00??????????????????????????:   /* ALU */
  35         32'b????00010?00????????00001001????:   /* Atomic swap */
  36         32'b????000100101111111111110001????:   /* Branch */
  37         32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
  38         32'b????000??1??????????00001??1????:   /* Halfword transfer - register offset */
  39         32'b????011????????????????????1????:   /* Undefined. I hate ARM */
  40         32'b????01??????????????????????????:   /* Single data transfer */
  41         32'b????100?????????????????????????:   /* Block data transfer */
  42         32'b????101?????????????????????????:   /* Branch */
  43         32'b????110?????????????????????????:   /* Coprocessor data transfer */
  44         32'b????1110???????????????????0????:   /* Coprocessor data op */
  45         32'b????1110???????????????????1????:   /* Coprocessor register transfer */
  46         32'b????1111????????????????????????:   /* SWI */
  47         default:                                /* X everything else out */
  48         endcase
  49 `endif
  50
  51         /* Flag setting */
  52         reg use_cpsr;
  53         reg [15:0] use_regs;
  54         reg def_cpsr;
  55         reg [15:0] def_regs;
  56
  57         function [15:0] idxbit;
  58                 input [3:0] r;
  59                 if (r == 15)
  60                         idxbit = 0;
  61                 else
  62                         idxbit = (16'b1) << r;
  63         endfunction
  64
  65         wire [3:0] rn = insn[19:16];
  66         wire [3:0] rd = insn[15:12];
  67         wire [3:0] rs = insn[11:8];
  68         wire [3:0] rm = insn[3:0];
  69         wire [3:0] cond = insn[31:28];
  70
  71         wire [3:0] rd_mul = insn[19:16];
  72         wire [3:0] rn_mul = insn[15:12];
  73         wire [3:0] rs_mul = insn[11:8];
  74
  75         wire [3:0] alu_opc = insn[24:21];
  76
  77         function alu_is_logical;
  78                 input [3:0] op;
  79
  80                 case (op)
  81                 `ALU_AND,`ALU_EOR,`ALU_TST,`ALU_TEQ,`ALU_ORR,`ALU_MOV,`ALU_BIC,`ALU_MVN: alu_is_logical = 1;
  82                 default: alu_is_logical = 0;
  83                 endcase
  84         endfunction
  85
  86         function alu_flags_only;
  87                 input [3:0] op;
  88
  89                 case (op)
  90                 `ALU_TST,`ALU_TEQ,`ALU_CMP,`ALU_CMN: alu_flags_only = 1;
  91                 default: alu_flags_only = 0;
  92                 endcase
  93         endfunction
  94
  95         function shift_requires_carry;
  96                 input [7:0] shift;
  97
  98                 case(shift[1:0])
  99                 `SHIFT_LSL: shift_requires_carry = (shift[7:2] == 0);
 100                 `SHIFT_LSR: shift_requires_carry = 0;
 101                 `SHIFT_ASR: shift_requires_carry = 0;
 102                 `SHIFT_ROR: shift_requires_carry = (shift[7:2] == 0);
 103                 endcase
 104         endfunction
 105
 106         always @(*)
 107                 casez (insn)
 108                 32'b????000000??????????????1001????:   /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */
 109                 begin
 110                         use_cpsr = `COND_MATTERS(cond);
 111                         use_regs = (insn[21] /* accum */ ? idxbit(rn_mul) : 0) | idxbit(rs_mul) | idxbit(rm);
 112                         def_cpsr = insn[20] /* setcc */;
 113                         def_regs = idxbit(rd_mul);
 114                 end
 115 //              32'b????00001???????????????1001????:   /* Multiply long */
 116                 32'b????00010?001111????000000000000:   /* MRS (Transfer PSR to register) */
 117                 begin
 118                         use_cpsr = `COND_MATTERS(cond) || (insn[22] == 0) /* Source = CPSR */;
 119                         use_regs = 0;
 120                         def_cpsr = 0;
 121                         def_regs = idxbit(rd);
 122                 end
 123                 32'b????00010?101001111100000000????:   /* MSR (Transfer register to PSR) */
 124                 begin
 125                         use_cpsr = `COND_MATTERS(cond);
 126                         use_regs = idxbit(rm);
 127                         def_cpsr = 1;
 128                         def_regs = 0;
 129                 end
 130                 32'b????00?10?1010001111????????????:   /* MSR (Transfer register or immediate to PSR, flag bits only) */
 131                 begin
 132                         use_cpsr = `COND_MATTERS(cond);
 133                         use_regs = insn[25] ? 0 : idxbit(rm);
 134                         def_cpsr = 1;
 135                         def_regs = 0;
 136                 end
 137                 32'b????00??????????????????????????:   /* ALU */
 138                 begin
 139                         use_cpsr = `COND_MATTERS(cond) | (!insn[25] /* I */ && shift_requires_carry(insn[11:4]));
 140                         use_regs =
 141                                 (insn[25] /* I */ ? 0 :
 142                                         (insn[4] /* shift by reg */ ?
 143                                                 (idxbit(rs) | idxbit(rm)) :
 144                                                 (idxbit(rm)))) |
 145                                 (((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0);
 146                         def_cpsr = insn[20] /* S */ | alu_is_logical(alu_opc);
 147                         def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd);
 148                 end
 149                 32'b????00010?00????????00001001????:   /* Atomic swap */
 150                 begin
 151                         use_cpsr = `COND_MATTERS(cond);
 152                         use_regs = idxbit(rn) | idxbit(rm);
 153                         def_cpsr = 0;
 154                         def_regs = idxbit(rd);
 155                 end
 156                 32'b????000100101111111111110001????:   /* Branch */
 157                 begin
 158                         use_cpsr = `COND_MATTERS(cond);
 159                         use_regs = idxbit(rm);
 160                         def_cpsr = 0;   // don't care, we'll never get there
 161                         def_regs = 0;
 162                 end
 163                 32'b????000??0??????????00001??1????:   /* Halfword transfer - register offset */
 164                 begin
 165                         use_cpsr = `COND_MATTERS(cond);
 166                         use_regs = idxbit(rn) | idxbit(rm) | (insn[20] /* L */ ? 0 : idxbit(rd));
 167                         def_cpsr = 0;
 168                         def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
 169                 end
 170                 32'b????000??1??????????00001??1????:   /* Halfword transfer - immediate offset */
 171                 begin
 172                         use_cpsr = `COND_MATTERS(cond);
 173                         use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : idxbit(rd));
 174                         def_cpsr = 0;
 175                         def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
 176                 end
 177                 32'b????011????????????????????1????:   /* Undefined. I hate ARM */
 178                 begin
 179                         use_cpsr = 0;
 180                         use_regs = 0;
 181                         def_cpsr = 0;
 182                         def_regs = 0;
 183                 end
 184                 32'b????100?????????????????????????:   /* Block data transfer */
 185                 begin
 186                         use_cpsr = `COND_MATTERS(cond);
 187                         use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : insn[15:0]);
 188                         def_cpsr = insn[22];    /* This is a superset of all cases, anyway. */
 189                         def_regs = (insn[21] /* W */ ? idxbit(rn) : 0) | (insn[20] /* L */ ? insn[15:0] : 0);
 190                 end
 191                 32'b????101?????????????????????????:   /* Branch */
 192                 begin
 193                         use_cpsr = `COND_MATTERS(cond);
 194                         use_regs = 0;
 195                         def_cpsr = 0;
 196                         def_regs = 0;
 197                 end
 198                 32'b????110?????????????????????????:   /* Coprocessor data transfer */
 199                 begin
 200                         use_cpsr = `COND_MATTERS(cond);
 201                         use_regs = idxbit(rn);
 202                         def_cpsr = 0;
 203                         def_regs = insn[21] /* W */ ? idxbit(rn) : 0;
 204                 end
 205                 32'b????1110???????????????????0????:   /* Coprocessor data op */
 206                 begin
 207                         use_cpsr = `COND_MATTERS(cond);
 208                         use_regs = 0;
 209                         def_cpsr = 0;
 210                         def_regs = 0;
 211                 end
 212                 32'b????1110???????????????????1????:   /* Coprocessor register transfer */
 213                 begin
 214                         use_cpsr = `COND_MATTERS(cond);
 215                         use_regs = insn[20] /* L */ ? 0 : idxbit(rd);
 216                         def_cpsr = 0;
 217                         def_regs = insn[20] /* L */ ? idxbit(rd) : 0;
 218                 end
 219                 32'b????1111????????????????????????:   /* SWI */
 220                 begin
 221                         use_cpsr = `COND_MATTERS(cond);
 222                         use_regs = 0;
 223                         def_cpsr = 0;
 224                         def_regs = 0;
 225                 end
 226                 default:                                /* X everything else out */
 227                 begin
 228                         use_cpsr = 1'bx;
 229                         use_regs = 16'bxxxxxxxxxxxxxxxx;
 230                         def_cpsr = 1'bx;
 231                         def_regs = 16'bxxxxxxxxxxxxxxxx;
 232                 end
 233                 endcase
 234
 235         /* Condition checking logic */
 236         reg condition_met;
 237         always @(*)
 238                 casez(insn[31:28])
 239                 `COND_EQ:       condition_met = cpsr[`CPSR_Z];
 240                 `COND_NE:       condition_met = !cpsr[`CPSR_Z];
 241                 `COND_CS:       condition_met = cpsr[`CPSR_C];
 242                 `COND_CC:       condition_met = !cpsr[`CPSR_C];
 243                 `COND_MI:       condition_met = cpsr[`CPSR_N];
 244                 `COND_PL:       condition_met = !cpsr[`CPSR_N];
 245                 `COND_VS:       condition_met = cpsr[`CPSR_V];
 246                 `COND_VC:       condition_met = !cpsr[`CPSR_V];
 247                 `COND_HI:       condition_met = cpsr[`CPSR_C] && !cpsr[`CPSR_Z];
 248                 `COND_LS:       condition_met = !cpsr[`CPSR_C] || cpsr[`CPSR_Z];
 249                 `COND_GE:       condition_met = cpsr[`CPSR_N] == cpsr[`CPSR_V];
 250                 `COND_LT:       condition_met = cpsr[`CPSR_N] != cpsr[`CPSR_V];
 251                 `COND_GT:       condition_met = !cpsr[`CPSR_Z] && (cpsr[`CPSR_N] == cpsr[`CPSR_V]);
 252                 `COND_LE:       condition_met = cpsr[`CPSR_Z] || (cpsr[`CPSR_N] != cpsr[`CPSR_V]);
 253                 `COND_AL:       condition_met = 1;
 254                 `COND_NV:       condition_met = 0;
 255                 default:        condition_met = 1'bx;
 256                 endcase
 257
 258         /* Issue logic */
 259         /* reg use_cpsr;
 260          * reg [15:0] use_regs;
 261          * reg def_cpsr;
 262          * reg [15:0] def_regs;
 263          */
 264
 265 endmodule