4 output reg [31:0] rdata_0,
6 output reg [31:0] rdata_1,
8 output reg [31:0] rdata_2,
10 output reg [31:0] rdata_3,
11 output reg [31:0] spsr,
14 input [31:0] write_data
17 reg [31:0] regfile [0:15];
20 regfile[4'h0] = 32'h00000005;
21 regfile[4'h1] = 32'h00000050;
22 regfile[4'h2] = 32'h00000500;
23 regfile[4'h3] = 32'h00005000;
24 regfile[4'h4] = 32'h00050000;
25 regfile[4'h5] = 32'h00500000;
26 regfile[4'h6] = 32'h05000000;
27 regfile[4'h7] = 32'h50000000;
28 regfile[4'h8] = 32'hA0000000;
29 regfile[4'h9] = 32'h0A000000;
30 regfile[4'hA] = 32'h00A00000;
31 regfile[4'hB] = 32'h000A0000;
32 regfile[4'hC] = 32'h0000A000;
33 regfile[4'hD] = 32'h00000A00;
34 regfile[4'hE] = 32'h000000A0;
35 regfile[4'hF] = 32'h00000000; /* Start off claiming we are in user mode. */
40 if ((read_0 == write) && write_req)
43 rdata_0 = regfile[read_0];
45 if ((read_1 == write) && write_req)
48 rdata_1 = regfile[read_1];
50 if ((read_2 == write) && write_req)
53 rdata_2 = regfile[read_2];
55 if ((read_3 == write) && write_req)
58 rdata_3 = regfile[read_3];
65 regfile[write] <= write_data;