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1 | module Writeback( | |
2 | input clk, | |
3 | ||
4 | input inbubble, | |
5 | ||
6 | input write_reg, | |
7 | input [3:0] write_num, | |
8 | input [31:0] write_data, | |
9 | ||
10 | input [31:0] cpsr, | |
11 | input [31:0] spsr, | |
12 | input cpsrup, | |
13 | ||
14 | output reg regfile_write, | |
15 | output reg [3:0] regfile_write_reg, | |
16 | output reg [31:0] regfile_write_data, | |
17 | ||
18 | output reg [31:0] outcpsr, | |
19 | output reg [31:0] outspsr, | |
20 | ||
21 | output reg jmp, | |
22 | output reg [31:0] jmppc); | |
23 | ||
24 | reg [31:0] last_outcpsr = 0, last_outspsr = 0; | |
25 | ||
26 | always @(*) | |
27 | if (inbubble || !cpsrup) | |
28 | outcpsr = last_outcpsr; | |
29 | else | |
30 | outcpsr = cpsr; | |
31 | ||
32 | always @(*) | |
33 | if (inbubble || !cpsrup) | |
34 | outspsr = last_outspsr; | |
35 | else | |
36 | outspsr = spsr; | |
37 | ||
38 | always @(*) | |
39 | begin | |
40 | regfile_write = 0; | |
41 | regfile_write_reg = 4'hx; | |
42 | regfile_write_data = 32'hxxxxxxxx; | |
43 | jmp = 0; | |
44 | jmppc = 32'h00000000; | |
45 | if (!inbubble) | |
46 | begin | |
47 | if (write_reg && (write_num != 15)) | |
48 | begin | |
49 | regfile_write = 1; | |
50 | regfile_write_reg = write_num; | |
51 | regfile_write_data = write_data; | |
52 | end else if (write_reg && (write_num == 15)) begin | |
53 | jmp = 1; | |
54 | jmppc = write_data; | |
55 | end | |
56 | end | |
57 | end | |
58 | ||
59 | always @(posedge clk) | |
60 | begin | |
61 | last_outspsr <= outspsr; | |
62 | last_outcpsr <= outcpsr; | |
63 | end | |
64 | endmodule |