| 1 | `include "ARM_Constants.v" |
| 2 | |
| 3 | module Issue( |
| 4 | input clk, |
| 5 | input Nrst, /* XXX not used yet */ |
| 6 | |
| 7 | input stall_1a, /* pipeline control */ |
| 8 | input flush_1a, |
| 9 | |
| 10 | input bubble_1a, /* stage inputs */ |
| 11 | input [31:0] insn_1a, |
| 12 | input [31:0] pc_1a, |
| 13 | input [31:0] cpsr_1a, |
| 14 | |
| 15 | output wire stall_0a, /* stage outputs */ |
| 16 | output reg bubble_2a = 1, |
| 17 | output reg [31:0] pc_2a = 0, |
| 18 | output reg [31:0] insn_2a = 0 |
| 19 | /* XXX other? */ |
| 20 | ); |
| 21 | |
| 22 | `ifdef COPY_PASTA_FODDER |
| 23 | /* from page 2 of ARM7TDMIvE2.pdf */ |
| 24 | casex (insn_1a) |
| 25 | `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ |
| 26 | // `DECODE_ALU_MUL_LONG: /* Multiply long */ |
| 27 | `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */ |
| 28 | `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */ |
| 29 | `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */ |
| 30 | `DECODE_ALU_SWP: /* Atomic swap */ |
| 31 | `DECODE_ALU_BX: /* Branch */ |
| 32 | `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */ |
| 33 | `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */ |
| 34 | `DECODE_ALU: /* ALU */ |
| 35 | `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */ |
| 36 | `DECODE_LDRSTR: /* Single data transfer */ |
| 37 | `DECODE_LDMSTM: /* Block data transfer */ |
| 38 | `DECODE_BRANCH: /* Branch */ |
| 39 | `DECODE_LDCSTC: /* Coprocessor data transfer */ |
| 40 | `DECODE_CDP: /* Coprocessor data op */ |
| 41 | `DECODE_MRCMCR: /* Coprocessor register transfer */ |
| 42 | `DECODE_SWI: /* SWI */ |
| 43 | default: /* X everything else out */ |
| 44 | endcase |
| 45 | `endif |
| 46 | |
| 47 | /* Flag setting */ |
| 48 | reg use_cpsr; |
| 49 | reg [15:0] use_regs; |
| 50 | reg def_cpsr; |
| 51 | reg [15:0] def_regs; |
| 52 | |
| 53 | function [15:0] idxbit; |
| 54 | input [3:0] r; |
| 55 | if (r == 15) |
| 56 | idxbit = 0; |
| 57 | else |
| 58 | idxbit = (16'b1) << r; |
| 59 | endfunction |
| 60 | |
| 61 | wire [3:0] rn = insn_1a[19:16]; |
| 62 | wire [3:0] rd = insn_1a[15:12]; |
| 63 | wire [3:0] rs = insn_1a[11:8]; |
| 64 | wire [3:0] rm = insn_1a[3:0]; |
| 65 | wire [3:0] cond = insn_1a[31:28]; |
| 66 | |
| 67 | wire [3:0] rd_mul = insn_1a[19:16]; |
| 68 | wire [3:0] rn_mul = insn_1a[15:12]; |
| 69 | wire [3:0] rs_mul = insn_1a[11:8]; |
| 70 | |
| 71 | wire [3:0] alu_opc = insn_1a[24:21]; |
| 72 | |
| 73 | function alu_is_logical; |
| 74 | input [3:0] op; |
| 75 | |
| 76 | case (op) |
| 77 | `ALU_AND,`ALU_EOR,`ALU_TST,`ALU_TEQ,`ALU_ORR,`ALU_MOV,`ALU_BIC,`ALU_MVN: alu_is_logical = 1; |
| 78 | default: alu_is_logical = 0; |
| 79 | endcase |
| 80 | endfunction |
| 81 | |
| 82 | function alu_flags_only; |
| 83 | input [3:0] op; |
| 84 | |
| 85 | case (op) |
| 86 | `ALU_TST,`ALU_TEQ,`ALU_CMP,`ALU_CMN: alu_flags_only = 1; |
| 87 | default: alu_flags_only = 0; |
| 88 | endcase |
| 89 | endfunction |
| 90 | |
| 91 | function shift_requires_carry; |
| 92 | input [7:0] shift; |
| 93 | |
| 94 | case(shift[1:0]) |
| 95 | `SHIFT_LSL: shift_requires_carry = (shift[7:2] == 0); |
| 96 | `SHIFT_LSR: shift_requires_carry = 0; |
| 97 | `SHIFT_ASR: shift_requires_carry = 0; |
| 98 | `SHIFT_ROR: shift_requires_carry = (shift[7:2] == 0); |
| 99 | endcase |
| 100 | endfunction |
| 101 | |
| 102 | always @(*) |
| 103 | casez (insn_1a) |
| 104 | `DECODE_ALU_MULT: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ |
| 105 | begin |
| 106 | use_cpsr = `COND_MATTERS(cond); |
| 107 | use_regs = (insn_1a[21] /* accum */ ? idxbit(rn_mul) : 0) | idxbit(rs_mul) | idxbit(rm); |
| 108 | def_cpsr = insn_1a[20] /* setcc */; |
| 109 | def_regs = idxbit(rd_mul); |
| 110 | end |
| 111 | // `DECODE_ALU_MUL_LONG: /* Multiply long */ |
| 112 | `DECODE_ALU_MRS: /* MRS (Transfer PSR to register) */ |
| 113 | begin |
| 114 | use_cpsr = `COND_MATTERS(cond) || (insn_1a[22] == 0) /* Source = CPSR */; |
| 115 | use_regs = 0; |
| 116 | def_cpsr = 0; |
| 117 | def_regs = idxbit(rd); |
| 118 | end |
| 119 | `DECODE_ALU_MSR: /* MSR (Transfer register to PSR) */ |
| 120 | begin |
| 121 | use_cpsr = `COND_MATTERS(cond); |
| 122 | use_regs = idxbit(rm); |
| 123 | def_cpsr = 1; |
| 124 | def_regs = 0; |
| 125 | end |
| 126 | `DECODE_ALU_MSR_FLAGS: /* MSR (Transfer register or immediate to PSR, flag bits only) */ |
| 127 | begin |
| 128 | use_cpsr = `COND_MATTERS(cond); |
| 129 | use_regs = insn_1a[25] ? 0 : idxbit(rm); |
| 130 | def_cpsr = 1; |
| 131 | def_regs = 0; |
| 132 | end |
| 133 | `DECODE_ALU_SWP: /* Atomic swap */ |
| 134 | begin |
| 135 | use_cpsr = `COND_MATTERS(cond); |
| 136 | use_regs = idxbit(rn) | idxbit(rm); |
| 137 | def_cpsr = 0; |
| 138 | def_regs = idxbit(rd); |
| 139 | end |
| 140 | `DECODE_ALU_BX: /* Branch */ |
| 141 | begin |
| 142 | use_cpsr = `COND_MATTERS(cond); |
| 143 | use_regs = idxbit(rm); |
| 144 | def_cpsr = 0; // don't care, we'll never get there |
| 145 | def_regs = 0; |
| 146 | end |
| 147 | `DECODE_ALU_HDATA_REG: /* Halfword transfer - register offset */ |
| 148 | begin |
| 149 | use_cpsr = `COND_MATTERS(cond); |
| 150 | use_regs = idxbit(rn) | idxbit(rm) | (insn_1a[20] /* L */ ? 0 : idxbit(rd)); |
| 151 | def_cpsr = 0; |
| 152 | def_regs = insn_1a[20] /* L */ ? idxbit(rd) : 0; |
| 153 | end |
| 154 | `DECODE_ALU_HDATA_IMM: /* Halfword transfer - immediate offset */ |
| 155 | begin |
| 156 | use_cpsr = `COND_MATTERS(cond); |
| 157 | use_regs = idxbit(rn) | (insn_1a[20] /* L */ ? 0 : idxbit(rd)); |
| 158 | def_cpsr = 0; |
| 159 | def_regs = insn_1a[20] /* L */ ? idxbit(rd) : 0; |
| 160 | end |
| 161 | `DECODE_ALU: /* ALU */ |
| 162 | begin |
| 163 | use_cpsr = `COND_MATTERS(cond) | (!insn_1a[25] /* I */ && shift_requires_carry(insn_1a[11:4])); |
| 164 | use_regs = |
| 165 | (insn_1a[25] /* I */ ? 0 : |
| 166 | (insn_1a[4] /* shift by reg */ ? |
| 167 | (idxbit(rs) | idxbit(rm)) : |
| 168 | (idxbit(rm)))) | |
| 169 | (((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0); |
| 170 | def_cpsr = insn_1a[20] /* S */; |
| 171 | def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd); |
| 172 | end |
| 173 | `DECODE_LDRSTR_UNDEFINED: /* Undefined. I hate ARM */ |
| 174 | begin |
| 175 | use_cpsr = 0; |
| 176 | use_regs = 0; |
| 177 | def_cpsr = 0; |
| 178 | def_regs = 0; |
| 179 | end |
| 180 | `DECODE_LDRSTR: |
| 181 | begin |
| 182 | use_cpsr = `COND_MATTERS(cond); |
| 183 | use_regs = idxbit(rn) | (insn_1a[25] /* I */ ? idxbit(rm) : 0) | (insn_1a[20] /* L */ ? 0 : idxbit(rd)); |
| 184 | def_cpsr = 0; |
| 185 | def_regs = insn_1a[20] /* L */ ? idxbit(rd) : 0; |
| 186 | end |
| 187 | `DECODE_LDMSTM: /* Block data transfer */ |
| 188 | begin |
| 189 | use_cpsr = `COND_MATTERS(cond); |
| 190 | use_regs = idxbit(rn) | (insn_1a[20] /* L */ ? 0 : insn_1a[15:0]); |
| 191 | def_cpsr = insn_1a[22]; /* This is a superset of all cases, anyway. */ |
| 192 | def_regs = (insn_1a[21] /* W */ ? idxbit(rn) : 0) | (insn_1a[20] /* L */ ? insn_1a[15:0] : 0); |
| 193 | end |
| 194 | `DECODE_BRANCH: /* Branch */ |
| 195 | begin |
| 196 | use_cpsr = `COND_MATTERS(cond); |
| 197 | use_regs = 0; |
| 198 | def_cpsr = 0; |
| 199 | def_regs = insn_1a[24] /* L */ ? (16'b1 << 14) : 0; |
| 200 | end |
| 201 | `DECODE_LDCSTC: /* Coprocessor data transfer */ |
| 202 | begin |
| 203 | use_cpsr = `COND_MATTERS(cond); |
| 204 | use_regs = idxbit(rn); |
| 205 | def_cpsr = 0; |
| 206 | def_regs = insn_1a[21] /* W */ ? idxbit(rn) : 0; |
| 207 | end |
| 208 | `DECODE_CDP: /* Coprocessor data op */ |
| 209 | begin |
| 210 | use_cpsr = `COND_MATTERS(cond); |
| 211 | use_regs = 0; |
| 212 | def_cpsr = 0; |
| 213 | def_regs = 0; |
| 214 | end |
| 215 | `DECODE_MRCMCR: /* Coprocessor register transfer */ |
| 216 | begin |
| 217 | use_cpsr = `COND_MATTERS(cond); |
| 218 | use_regs = insn_1a[20] /* L */ ? 0 : idxbit(rd); |
| 219 | def_cpsr = 0; |
| 220 | def_regs = insn_1a[20] /* L */ ? idxbit(rd) : 0; |
| 221 | end |
| 222 | `DECODE_SWI: /* SWI */ |
| 223 | begin |
| 224 | use_cpsr = `COND_MATTERS(cond); |
| 225 | use_regs = 0; |
| 226 | def_cpsr = 0; |
| 227 | def_regs = 0; |
| 228 | end |
| 229 | default: /* X everything else out */ |
| 230 | begin |
| 231 | use_cpsr = 1'bx; |
| 232 | use_regs = 16'bxxxxxxxxxxxxxxxx; |
| 233 | def_cpsr = 1'bx; |
| 234 | def_regs = 16'bxxxxxxxxxxxxxxxx; |
| 235 | end |
| 236 | endcase |
| 237 | |
| 238 | /* Condition checking logic */ |
| 239 | reg condition_met_1a; |
| 240 | always @(*) |
| 241 | casez(insn_1a[31:28]) |
| 242 | `COND_EQ: condition_met_1a = cpsr_1a[`CPSR_Z]; |
| 243 | `COND_NE: condition_met_1a = !cpsr_1a[`CPSR_Z]; |
| 244 | `COND_CS: condition_met_1a = cpsr_1a[`CPSR_C]; |
| 245 | `COND_CC: condition_met_1a = !cpsr_1a[`CPSR_C]; |
| 246 | `COND_MI: condition_met_1a = cpsr_1a[`CPSR_N]; |
| 247 | `COND_PL: condition_met_1a = !cpsr_1a[`CPSR_N]; |
| 248 | `COND_VS: condition_met_1a = cpsr_1a[`CPSR_V]; |
| 249 | `COND_VC: condition_met_1a = !cpsr_1a[`CPSR_V]; |
| 250 | `COND_HI: condition_met_1a = cpsr_1a[`CPSR_C] && !cpsr_1a[`CPSR_Z]; |
| 251 | `COND_LS: condition_met_1a = !cpsr_1a[`CPSR_C] || cpsr_1a[`CPSR_Z]; |
| 252 | `COND_GE: condition_met_1a = cpsr_1a[`CPSR_N] == cpsr_1a[`CPSR_V]; |
| 253 | `COND_LT: condition_met_1a = cpsr_1a[`CPSR_N] != cpsr_1a[`CPSR_V]; |
| 254 | `COND_GT: condition_met_1a = !cpsr_1a[`CPSR_Z] && (cpsr_1a[`CPSR_N] == cpsr_1a[`CPSR_V]); |
| 255 | `COND_LE: condition_met_1a = cpsr_1a[`CPSR_Z] || (cpsr_1a[`CPSR_N] != cpsr_1a[`CPSR_V]); |
| 256 | `COND_AL: condition_met_1a = 1; |
| 257 | `COND_NV: condition_met_1a = 0; |
| 258 | default: condition_met_1a = 1'bx; |
| 259 | endcase |
| 260 | |
| 261 | /* Issue logic */ |
| 262 | /* Once it's hit writeback, it's hit the regfile via forwarding so you're done. */ |
| 263 | reg cpsr_inflight_2a = 0, cpsr_inflight_3a = 0; |
| 264 | reg [15:0] regs_inflight_2a = 0, regs_inflight_3a = 0; |
| 265 | |
| 266 | wire waiting_cpsr_1a = use_cpsr & (cpsr_inflight_2a | cpsr_inflight_3a); |
| 267 | wire waiting_regs_1a = |(use_regs & (regs_inflight_2a | regs_inflight_3a)); |
| 268 | wire waiting_1a = waiting_cpsr_1a | waiting_regs_1a; |
| 269 | assign stall_0a = (waiting_1a && !bubble_1a && !flush_1a) || stall_1a; |
| 270 | |
| 271 | reg delayedflush_1a = 0; |
| 272 | always @(posedge clk/* or negedge Nrst*/) |
| 273 | if (!Nrst) |
| 274 | delayedflush_1a <= 0; |
| 275 | else if (flush_1a && stall_0a /* halp! I can't do it now, maybe later? */) |
| 276 | delayedflush_1a <= 1; |
| 277 | else if (!stall_0a /* anything has been handled this time around */) |
| 278 | delayedflush_1a <= 0; |
| 279 | |
| 280 | /* Actually do the issue. */ |
| 281 | always @(posedge clk or negedge Nrst) |
| 282 | begin |
| 283 | if (waiting_1a) |
| 284 | $display("ISSUE: Stalling instruction %08x because %d/%d", insn_1a, waiting_cpsr_1a, waiting_regs_1a); |
| 285 | |
| 286 | if (!Nrst) begin |
| 287 | bubble_2a <= 1; |
| 288 | /*AUTORESET*/ |
| 289 | // Beginning of autoreset for uninitialized flops |
| 290 | cpsr_inflight_2a <= 1'h0; |
| 291 | cpsr_inflight_3a <= 1'h0; |
| 292 | insn_2a <= 32'h0; |
| 293 | pc_2a <= 32'h0; |
| 294 | regs_inflight_2a <= 16'h0; |
| 295 | regs_inflight_3a <= 16'h0; |
| 296 | // End of automatics |
| 297 | end else if (!stall_1a) |
| 298 | begin |
| 299 | cpsr_inflight_3a <= cpsr_inflight_2a; /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */ |
| 300 | cpsr_inflight_2a <= (waiting_1a || bubble_1a || !condition_met_1a) ? 0 : def_cpsr; |
| 301 | regs_inflight_3a <= regs_inflight_2a; |
| 302 | regs_inflight_2a <= (waiting_1a || bubble_1a || !condition_met_1a) ? 0 : def_regs; |
| 303 | |
| 304 | bubble_2a <= bubble_1a | waiting_1a | !condition_met_1a | flush_1a | delayedflush_1a; |
| 305 | pc_2a <= pc_1a; |
| 306 | insn_2a <= insn_1a; |
| 307 | end |
| 308 | end |
| 309 | endmodule |