Add chip enable correctness for CellularRAM.
[firearm.git] / ICache.v
... / ...
CommitLineData
1/* 16 cache entries, 64-byte long cache lines */
2
3module ICache(
4 input clk,
5
6 /* ARM core interface */
7 input [31:0] ic__rd_addr_0a,
8 input ic__rd_req_0a,
9 output wire ic__rd_wait_0a,
10 output wire [31:0] ic__rd_data_1a,
11
12 /* bus interface */
13 output wire bus_req,
14 input bus_ack,
15 output reg [31:0] bus_addr,
16 input [31:0] bus_rdata,
17 output wire [31:0] bus_wdata,
18 output reg bus_rd,
19 output wire bus_wr,
20 input bus_ready);
21
22 assign bus_wr = 0;
23 assign bus_wdata = 0;
24
25 wire [31:0] rd_addr_0a;
26 wire rd_req_0a;
27 reg rd_wait_0a;
28 reg [31:0] rd_data_1a;
29 assign ic__rd_wait_0a = rd_wait_0a;
30 assign ic__rd_data_1a = rd_data_1a;
31 assign rd_addr_0a = ic__rd_addr_0a;
32 assign rd_req_0a = ic__rd_req_0a;
33
34 /* [31 tag 10] [9 cache index 6] [5 data index 0]
35 * so the data index is 6 bits long
36 * so the cache index is 4 bits long
37 * so the tag is 22 bits long. c.c
38 */
39
40 reg cache_valid [15:0];
41 reg [21:0] cache_tags [15:0];
42 reg [31:0] cache_data [255:0 /* {line, word} */]; //synthesis attribute ram_style of cache_data is block
43
44 integer i;
45 initial
46 for (i = 0; i < 16; i = i + 1)
47 begin
48 cache_valid[i[3:0]] = 0;
49 cache_tags[i[3:0]] = 0;
50 end
51
52 wire [5:0] rd_didx_0a = rd_addr_0a[5:0];
53 wire [3:0] rd_didx_word_0a = rd_didx_0a[5:2];
54 wire [3:0] rd_idx_0a = rd_addr_0a[9:6];
55 wire [21:0] rd_tag_0a = rd_addr_0a[31:10];
56
57 reg [31:0] rd_addr_1a = 32'hFFFFFFFF;
58
59 wire cache_hit_0a = cache_valid[rd_idx_0a] && (cache_tags[rd_idx_0a] == rd_tag_0a);
60
61 reg [3:0] cache_fill_pos_0a = 0;
62 assign bus_req = rd_req_0a && !cache_hit_0a; /* xxx, needed for Verilator */
63 always @(*)
64 if (rd_req_0a && !cache_hit_0a && bus_ack) begin
65 bus_addr = {rd_addr_0a[31:6], cache_fill_pos_0a[3:0], 2'b00 /* reads are 32-bits */};
66 bus_rd = 1;
67 end else begin
68 bus_addr = 0;
69 bus_rd = 0;
70 end
71
72 always @(*) begin
73 rd_wait_0a = rd_req_0a && !cache_hit_0a;
74 end
75
76 always @(posedge clk) begin
77 // Do the actual read.
78 rd_data_1a <= cache_data[{rd_idx_0a,rd_didx_word_0a}];
79
80 rd_addr_1a <= {rd_addr_0a[31:6], 6'b0};
81 if (cache_fill_pos_0a != 0 && ((rd_addr_1a != {rd_addr_0a[31:6], 6'b0}) || cache_hit_0a)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
82 cache_fill_pos_0a <= 0;
83 else if (rd_req_0a && !cache_hit_0a && bus_ack && bus_ready) begin
84 $display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr_0a, bus_addr, bus_rdata);
85 cache_data[{rd_idx_0a,cache_fill_pos_0a}] <= bus_rdata;
86 cache_fill_pos_0a <= cache_fill_pos_0a + 1;
87 if (cache_fill_pos_0a == 15) begin /* Done? */
88 cache_tags[rd_idx_0a] <= rd_tag_0a;
89 cache_valid[rd_idx_0a] <= 1;
90 $display("ICACHE: Fill complete for line %x, tag %x", rd_idx_0a, rd_tag_0a);
91 end else
92 cache_valid[rd_idx_0a] <= 0;
93 end
94 end
95endmodule
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