RegFile: Move to assigns, since XST can't always @(regfile).
[firearm.git] / ICache.v
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1/* 16 cache entries, 64-byte long cache lines */
2
3module ICache(
4 input clk,
5
6 /* ARM core interface */
7 input [31:0] rd_addr,
8 input rd_req,
9 output reg rd_wait,
10 output reg [31:0] rd_data,
11
12 /* bus interface */
13 output wire bus_req,
14 input bus_ack,
15 output reg [31:0] bus_addr,
16 input [31:0] bus_rdata,
17 output wire [31:0] bus_wdata,
18 output reg bus_rd,
19 output wire bus_wr,
20 input bus_ready);
21
22 assign bus_wr = 0;
23 assign bus_wdata = 0;
24
25 /* [31 tag 10] [9 cache index 6] [5 data index 0]
26 * so the data index is 6 bits long
27 * so the cache index is 4 bits long
28 * so the tag is 22 bits long. c.c
29 */
30
31 reg cache_valid [15:0];
32 reg [21:0] cache_tags [15:0];
33 reg [31:0] cache_data [15:0 /* line */] [15:0 /* word */];
34
35 integer i;
36 initial
37 for (i = 0; i < 16; i = i + 1)
38 begin
39 cache_valid[i[3:0]] = 0;
40 cache_tags[i[3:0]] = 0;
41 end
42
43 wire [5:0] rd_didx = rd_addr[5:0];
44 wire [3:0] rd_didx_word = rd_didx[5:2];
45 wire [3:0] rd_idx = rd_addr[9:6];
46 wire [21:0] rd_tag = rd_addr[31:10];
47
48 reg [31:0] prev_rd_addr = 32'hFFFFFFFF;
49
50 wire cache_hit = cache_valid[rd_idx] && (cache_tags[rd_idx] == rd_tag);
51
52 wire [31:0] curdata = cache_data[rd_idx][rd_didx_word];
53 always @(*) begin
54 rd_wait = rd_req && !cache_hit;
55 rd_data = curdata;
56 end
57
58 reg [3:0] cache_fill_pos = 0;
59 assign bus_req = rd_req && !cache_hit; /* xxx, needed for Verilator */
60 always @(*)
61 if (rd_req && !cache_hit && bus_ack) begin
62 bus_addr = {rd_addr[31:6], cache_fill_pos[3:0], 2'b00 /* reads are 32-bits */};
63 bus_rd = 1;
64 end else begin
65 bus_addr = 0;
66 bus_rd = 0;
67 end
68
69 always @(posedge clk) begin
70 prev_rd_addr <= {rd_addr[31:6], 6'b0};
71 if (cache_fill_pos != 0 && ((prev_rd_addr != {rd_addr[31:6], 6'b0}) || cache_hit)) /* If this wasn't from the same line, or we've moved on somehow, reset the fill circuitry. */
72 cache_fill_pos <= 0;
73 else if (rd_req && !cache_hit) begin
74 if (bus_ack && bus_ready) begin /* Started the fill, and we have data. */
75 $display("ICACHE: FILL: rd addr %08x; bus addr %08x; bus data %08x", rd_addr, bus_addr, bus_rdata);
76 cache_data[rd_idx][cache_fill_pos] <= bus_rdata;
77 cache_fill_pos <= cache_fill_pos + 1;
78 if (cache_fill_pos == 15) begin /* Done? */
79 cache_tags[rd_idx] <= rd_tag;
80 cache_valid[rd_idx] <= 1;
81 $display("ICACHE: Fill complete for line %x, tag %x", rd_idx, rd_tag);
82 end else
83 cache_valid[rd_idx] <= 0;
84 end
85 end
86 end
87endmodule
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