| 1 | `include "ARM_Constants.v" |
| 2 | |
| 3 | module Issue( |
| 4 | input clk, |
| 5 | input Nrst, /* XXX not used yet */ |
| 6 | |
| 7 | input stall, /* pipeline control */ |
| 8 | input flush, |
| 9 | |
| 10 | input inbubble, /* stage inputs */ |
| 11 | input [31:0] insn, |
| 12 | input [31:0] inpc, |
| 13 | input [31:0] cpsr, |
| 14 | |
| 15 | output reg outstall = 0, /* stage outputs */ |
| 16 | output reg outbubble = 1, |
| 17 | output reg [31:0] outpc = 0, |
| 18 | output reg [31:0] outinsn = 0 |
| 19 | /* XXX other? */ |
| 20 | ); |
| 21 | |
| 22 | |
| 23 | |
| 24 | `ifdef COPY_PASTA_FODDER |
| 25 | /* from page 2 of ARM7TDMIvE2.pdf */ |
| 26 | casex (insn) |
| 27 | 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ |
| 28 | // 32'b????00001???????????????1001????: /* Multiply long */ |
| 29 | 32'b????00010?001111????000000000000: /* MRS (Transfer PSR to register) */ |
| 30 | 32'b????00010?101001111100000000????: /* MSR (Transfer register to PSR) */ |
| 31 | 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */ |
| 32 | 32'b????00??????????????????????????: /* ALU */ |
| 33 | 32'b????00010?00????????00001001????: /* Atomic swap */ |
| 34 | 32'b????000100101111111111110001????: /* Branch */ |
| 35 | 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */ |
| 36 | 32'b????000??1??????????00001??1????: /* Halfword transfer - register offset */ |
| 37 | 32'b????011????????????????????1????: /* Undefined. I hate ARM */ |
| 38 | 32'b????01??????????????????????????: /* Single data transfer */ |
| 39 | 32'b????100?????????????????????????: /* Block data transfer */ |
| 40 | 32'b????101?????????????????????????: /* Branch */ |
| 41 | 32'b????110?????????????????????????: /* Coprocessor data transfer */ |
| 42 | 32'b????1110???????????????????0????: /* Coprocessor data op */ |
| 43 | 32'b????1110???????????????????1????: /* Coprocessor register transfer */ |
| 44 | 32'b????1111????????????????????????: /* SWI */ |
| 45 | default: /* X everything else out */ |
| 46 | endcase |
| 47 | `endif |
| 48 | |
| 49 | /* Flag setting */ |
| 50 | reg use_cpsr; |
| 51 | reg [15:0] use_regs; |
| 52 | reg def_cpsr; |
| 53 | reg [15:0] def_regs; |
| 54 | |
| 55 | function [15:0] idxbit; |
| 56 | input [3:0] r; |
| 57 | if (r == 15) |
| 58 | idxbit = 0; |
| 59 | else |
| 60 | idxbit = (16'b1) << r; |
| 61 | endfunction |
| 62 | |
| 63 | wire [3:0] rn = insn[19:16]; |
| 64 | wire [3:0] rd = insn[15:12]; |
| 65 | wire [3:0] rs = insn[11:8]; |
| 66 | wire [3:0] rm = insn[3:0]; |
| 67 | wire [3:0] cond = insn[31:28]; |
| 68 | |
| 69 | wire [3:0] rd_mul = insn[19:16]; |
| 70 | wire [3:0] rn_mul = insn[15:12]; |
| 71 | wire [3:0] rs_mul = insn[11:8]; |
| 72 | |
| 73 | wire [3:0] alu_opc = insn[24:21]; |
| 74 | |
| 75 | function alu_is_logical; |
| 76 | input [3:0] op; |
| 77 | |
| 78 | case (op) |
| 79 | `ALU_AND,`ALU_EOR,`ALU_TST,`ALU_TEQ,`ALU_ORR,`ALU_MOV,`ALU_BIC,`ALU_MVN: alu_is_logical = 1; |
| 80 | default: alu_is_logical = 0; |
| 81 | endcase |
| 82 | endfunction |
| 83 | |
| 84 | function alu_flags_only; |
| 85 | input [3:0] op; |
| 86 | |
| 87 | case (op) |
| 88 | `ALU_TST,`ALU_TEQ,`ALU_CMP,`ALU_CMN: alu_flags_only = 1; |
| 89 | default: alu_flags_only = 0; |
| 90 | endcase |
| 91 | endfunction |
| 92 | |
| 93 | function shift_requires_carry; |
| 94 | input [7:0] shift; |
| 95 | |
| 96 | case(shift[1:0]) |
| 97 | `SHIFT_LSL: shift_requires_carry = (shift[7:2] == 0); |
| 98 | `SHIFT_LSR: shift_requires_carry = 0; |
| 99 | `SHIFT_ASR: shift_requires_carry = 0; |
| 100 | `SHIFT_ROR: shift_requires_carry = (shift[7:2] == 0); |
| 101 | endcase |
| 102 | endfunction |
| 103 | |
| 104 | always @(*) |
| 105 | casez (insn) |
| 106 | 32'b????000000??????????????1001????: /* Multiply -- must come before ALU, because it pattern matches a specific case of ALU */ |
| 107 | begin |
| 108 | use_cpsr = `COND_MATTERS(cond); |
| 109 | use_regs = (insn[21] /* accum */ ? idxbit(rn_mul) : 0) | idxbit(rs_mul) | idxbit(rm); |
| 110 | def_cpsr = insn[20] /* setcc */; |
| 111 | def_regs = idxbit(rd_mul); |
| 112 | end |
| 113 | // 32'b????00001???????????????1001????: /* Multiply long */ |
| 114 | 32'b????00010?001111????000000000000: /* MRS (Transfer PSR to register) */ |
| 115 | begin |
| 116 | use_cpsr = `COND_MATTERS(cond) || (insn[22] == 0) /* Source = CPSR */; |
| 117 | use_regs = 0; |
| 118 | def_cpsr = 0; |
| 119 | def_regs = idxbit(rd); |
| 120 | end |
| 121 | 32'b????00010?101001111100000000????: /* MSR (Transfer register to PSR) */ |
| 122 | begin |
| 123 | use_cpsr = `COND_MATTERS(cond); |
| 124 | use_regs = idxbit(rm); |
| 125 | def_cpsr = 1; |
| 126 | def_regs = 0; |
| 127 | end |
| 128 | 32'b????00?10?1010001111????????????: /* MSR (Transfer register or immediate to PSR, flag bits only) */ |
| 129 | begin |
| 130 | use_cpsr = `COND_MATTERS(cond); |
| 131 | use_regs = insn[25] ? 0 : idxbit(rm); |
| 132 | def_cpsr = 1; |
| 133 | def_regs = 0; |
| 134 | end |
| 135 | 32'b????00??????????????????????????: /* ALU */ |
| 136 | begin |
| 137 | use_cpsr = `COND_MATTERS(cond) | (!insn[25] /* I */ && shift_requires_carry(insn[11:4])); |
| 138 | use_regs = |
| 139 | (insn[25] /* I */ ? 0 : |
| 140 | (insn[4] /* shift by reg */ ? |
| 141 | (idxbit(rs) | idxbit(rm)) : |
| 142 | (idxbit(rm)))) | |
| 143 | (((alu_opc != `ALU_MOV) && (alu_opc != `ALU_MVN)) ? idxbit(rn) : 0); |
| 144 | def_cpsr = insn[20] /* S */ | alu_is_logical(alu_opc); |
| 145 | def_regs = alu_flags_only(alu_opc) ? 0 : idxbit(rd); |
| 146 | end |
| 147 | 32'b????00010?00????????00001001????: /* Atomic swap */ |
| 148 | begin |
| 149 | use_cpsr = `COND_MATTERS(cond); |
| 150 | use_regs = idxbit(rn) | idxbit(rm); |
| 151 | def_cpsr = 0; |
| 152 | def_regs = idxbit(rd); |
| 153 | end |
| 154 | 32'b????000100101111111111110001????: /* Branch */ |
| 155 | begin |
| 156 | use_cpsr = `COND_MATTERS(cond); |
| 157 | use_regs = idxbit(rm); |
| 158 | def_cpsr = 0; // don't care, we'll never get there |
| 159 | def_regs = 0; |
| 160 | end |
| 161 | 32'b????000??0??????????00001??1????: /* Halfword transfer - register offset */ |
| 162 | begin |
| 163 | use_cpsr = `COND_MATTERS(cond); |
| 164 | use_regs = idxbit(rn) | idxbit(rm) | (insn[20] /* L */ ? 0 : idxbit(rd)); |
| 165 | def_cpsr = 0; |
| 166 | def_regs = insn[20] /* L */ ? idxbit(rd) : 0; |
| 167 | end |
| 168 | 32'b????000??1??????????00001??1????: /* Halfword transfer - immediate offset */ |
| 169 | begin |
| 170 | use_cpsr = `COND_MATTERS(cond); |
| 171 | use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : idxbit(rd)); |
| 172 | def_cpsr = 0; |
| 173 | def_regs = insn[20] /* L */ ? idxbit(rd) : 0; |
| 174 | end |
| 175 | 32'b????011????????????????????1????: /* Undefined. I hate ARM */ |
| 176 | begin |
| 177 | use_cpsr = 0; |
| 178 | use_regs = 0; |
| 179 | def_cpsr = 0; |
| 180 | def_regs = 0; |
| 181 | end |
| 182 | 32'b????100?????????????????????????: /* Block data transfer */ |
| 183 | begin |
| 184 | use_cpsr = `COND_MATTERS(cond); |
| 185 | use_regs = idxbit(rn) | (insn[20] /* L */ ? 0 : insn[15:0]); |
| 186 | def_cpsr = insn[22]; /* This is a superset of all cases, anyway. */ |
| 187 | def_regs = (insn[21] /* W */ ? idxbit(rn) : 0) | (insn[20] /* L */ ? insn[15:0] : 0); |
| 188 | end |
| 189 | 32'b????101?????????????????????????: /* Branch */ |
| 190 | begin |
| 191 | use_cpsr = `COND_MATTERS(cond); |
| 192 | use_regs = 0; |
| 193 | def_cpsr = 0; |
| 194 | def_regs = 0; |
| 195 | end |
| 196 | 32'b????110?????????????????????????: /* Coprocessor data transfer */ |
| 197 | begin |
| 198 | use_cpsr = `COND_MATTERS(cond); |
| 199 | use_regs = idxbit(rn); |
| 200 | def_cpsr = 0; |
| 201 | def_regs = insn[21] /* W */ ? idxbit(rn) : 0; |
| 202 | end |
| 203 | 32'b????1110???????????????????0????: /* Coprocessor data op */ |
| 204 | begin |
| 205 | use_cpsr = `COND_MATTERS(cond); |
| 206 | use_regs = 0; |
| 207 | def_cpsr = 0; |
| 208 | def_regs = 0; |
| 209 | end |
| 210 | 32'b????1110???????????????????1????: /* Coprocessor register transfer */ |
| 211 | begin |
| 212 | use_cpsr = `COND_MATTERS(cond); |
| 213 | use_regs = insn[20] /* L */ ? 0 : idxbit(rd); |
| 214 | def_cpsr = 0; |
| 215 | def_regs = insn[20] /* L */ ? idxbit(rd) : 0; |
| 216 | end |
| 217 | 32'b????1111????????????????????????: /* SWI */ |
| 218 | begin |
| 219 | use_cpsr = `COND_MATTERS(cond); |
| 220 | use_regs = 0; |
| 221 | def_cpsr = 0; |
| 222 | def_regs = 0; |
| 223 | end |
| 224 | default: /* X everything else out */ |
| 225 | begin |
| 226 | use_cpsr = 1'bx; |
| 227 | use_regs = 16'bxxxxxxxxxxxxxxxx; |
| 228 | def_cpsr = 1'bx; |
| 229 | def_regs = 16'bxxxxxxxxxxxxxxxx; |
| 230 | end |
| 231 | endcase |
| 232 | |
| 233 | /* Condition checking logic */ |
| 234 | reg condition_met; |
| 235 | always @(*) |
| 236 | casez(insn[31:28]) |
| 237 | `COND_EQ: condition_met = cpsr[`CPSR_Z]; |
| 238 | `COND_NE: condition_met = !cpsr[`CPSR_Z]; |
| 239 | `COND_CS: condition_met = cpsr[`CPSR_C]; |
| 240 | `COND_CC: condition_met = !cpsr[`CPSR_C]; |
| 241 | `COND_MI: condition_met = cpsr[`CPSR_N]; |
| 242 | `COND_PL: condition_met = !cpsr[`CPSR_N]; |
| 243 | `COND_VS: condition_met = cpsr[`CPSR_V]; |
| 244 | `COND_VC: condition_met = !cpsr[`CPSR_V]; |
| 245 | `COND_HI: condition_met = cpsr[`CPSR_C] && !cpsr[`CPSR_Z]; |
| 246 | `COND_LS: condition_met = !cpsr[`CPSR_C] || cpsr[`CPSR_Z]; |
| 247 | `COND_GE: condition_met = cpsr[`CPSR_N] == cpsr[`CPSR_V]; |
| 248 | `COND_LT: condition_met = cpsr[`CPSR_N] != cpsr[`CPSR_V]; |
| 249 | `COND_GT: condition_met = !cpsr[`CPSR_Z] && (cpsr[`CPSR_N] == cpsr[`CPSR_V]); |
| 250 | `COND_LE: condition_met = cpsr[`CPSR_Z] || (cpsr[`CPSR_N] != cpsr[`CPSR_V]); |
| 251 | `COND_AL: condition_met = 1; |
| 252 | `COND_NV: condition_met = 0; |
| 253 | default: condition_met = 1'bx; |
| 254 | endcase |
| 255 | |
| 256 | /* Issue logic */ |
| 257 | `define STAGE_EXECUTE 0 |
| 258 | `define STAGE_MEMORY 1 |
| 259 | /* Once it's hit writeback, it's essentially hit the regfile so you're done. */ |
| 260 | reg cpsr_inflight [1:0]; |
| 261 | reg [15:0] regs_inflight [1:0]; |
| 262 | |
| 263 | reg waiting_cpsr; |
| 264 | reg waiting_regs; |
| 265 | wire waiting = waiting_cpsr | waiting_regs; |
| 266 | |
| 267 | initial |
| 268 | begin |
| 269 | cpsr_inflight[0] = 0; |
| 270 | cpsr_inflight[1] = 0; |
| 271 | regs_inflight[0] = 0; |
| 272 | regs_inflight[1] = 0; |
| 273 | end |
| 274 | |
| 275 | always @(*) |
| 276 | begin |
| 277 | waiting_cpsr = use_cpsr & (cpsr_inflight[0] | cpsr_inflight[1]); |
| 278 | waiting_regs = |(use_regs & (regs_inflight[0] | regs_inflight[1])); |
| 279 | |
| 280 | outstall = waiting && !inbubble; /* Happens in an always @*, because it is an exception. */ |
| 281 | end |
| 282 | |
| 283 | /* Actually do the issue. */ |
| 284 | always @(posedge clk) |
| 285 | begin |
| 286 | cpsr_inflight[0] <= cpsr_inflight[1]; /* I'm not sure how well selects work with arrays, and that seems like a dumb thing to get anusulated by. */ |
| 287 | cpsr_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_cpsr; |
| 288 | regs_inflight[0] <= regs_inflight[1]; |
| 289 | regs_inflight[1] <= (waiting || inbubble || !condition_met) ? 0 : def_regs; |
| 290 | |
| 291 | if (waiting) |
| 292 | begin |
| 293 | $display("ISSUE: Stalling instruction %08x because %d/%d", insn, waiting_cpsr, waiting_regs); |
| 294 | end |
| 295 | |
| 296 | outbubble <= inbubble | waiting | !condition_met; |
| 297 | outpc <= inpc; |
| 298 | outinsn <= insn; |
| 299 | end |
| 300 | endmodule |