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1`include "ARM_Constants.v"
2
3module Memory(
4 input clk,
5 input Nrst,
6
7 input flush,
8
9 /* bus interface */
10 output reg [31:0] busaddr,
11 output reg rd_req,
12 output reg wr_req,
13 input rw_wait,
14 output reg [31:0] wr_data,
15 input [31:0] rd_data,
16 output reg [2:0] data_size,
17
18 /* regfile interface */
19 output reg [3:0] st_read,
20 input [31:0] st_data,
21
22 /* Coprocessor interface */
23 output reg cp_req,
24 input cp_ack,
25 input cp_busy,
26 output reg cp_rnw, /* 1 = read from CP, 0 = write to CP */
27 input [31:0] cp_read,
28 output reg [31:0] cp_write,
29
30 /* stage inputs */
31 input inbubble,
32 input [31:0] pc,
33 input [31:0] insn,
34 input [31:0] op0,
35 input [31:0] op1,
36 input [31:0] op2,
37 input [31:0] spsr,
38 input [31:0] cpsr,
39 input cpsrup,
40 input write_reg,
41 input [3:0] write_num,
42 input [31:0] write_data,
43
44 /* outputs */
45 output reg outstall,
46 output reg outbubble,
47 output reg [31:0] outpc,
48 output reg [31:0] outinsn,
49 output reg out_write_reg = 1'b0,
50 output reg [3:0] out_write_num = 4'bxxxx,
51 output reg [31:0] out_write_data = 32'hxxxxxxxx,
52 output reg [31:0] outspsr = 32'hxxxxxxxx,
53 output reg [31:0] outcpsr = 32'hxxxxxxxx,
54 output reg outcpsrup = 1'hx
55 );
56
57 reg [31:0] addr, raddr, prev_raddr, next_regdata, next_outcpsr;
58 reg next_outcpsrup;
59 reg [31:0] prevaddr;
60 reg [3:0] next_regsel, cur_reg, prev_reg;
61 reg next_writeback;
62
63 reg next_outbubble;
64 reg next_write_reg;
65 reg [3:0] next_write_num;
66 reg [31:0] next_write_data;
67
68 reg [3:0] lsr_state = 4'b0001, next_lsr_state;
69 reg [31:0] align_s1, align_s2, align_rddata;
70
71 reg [2:0] lsrh_state = 3'b001, next_lsrh_state;
72 reg [31:0] lsrh_rddata;
73 reg [15:0] lsrh_rddata_s1;
74 reg [7:0] lsrh_rddata_s2;
75
76 reg [15:0] regs, next_regs;
77 reg [3:0] lsm_state = 4'b0001, next_lsm_state;
78 reg [5:0] offset, prev_offset, offset_sel;
79
80 reg [31:0] swp_oldval, next_swp_oldval;
81 reg [1:0] swp_state = 2'b01, next_swp_state;
82
83 reg do_rd_data_latch;
84 reg [31:0] rd_data_latch = 32'hxxxxxxxx;
85
86 always @(posedge clk)
87 begin
88 outpc <= pc;
89 outinsn <= insn;
90 outbubble <= next_outbubble;
91 out_write_reg <= next_write_reg;
92 out_write_num <= next_write_num;
93 out_write_data <= next_write_data;
94 regs <= next_regs;
95 prev_reg <= cur_reg;
96 if (!rw_wait)
97 prev_offset <= offset;
98 prev_raddr <= raddr;
99 outcpsr <= next_outcpsr;
100 outspsr <= spsr;
101 outcpsrup <= next_outcpsrup;
102 swp_state <= next_swp_state;
103 lsm_state <= next_lsm_state;
104 lsr_state <= next_lsr_state;
105 lsrh_state <= next_lsrh_state;
106 if (do_rd_data_latch)
107 rd_data_latch <= rd_data;
108 prevaddr <= addr;
109 end
110
111 reg delayedflush = 0;
112 always @(posedge clk)
113 if (flush && outstall /* halp! I can't do it now, maybe later? */)
114 delayedflush <= 1;
115 else if (!outstall /* anything has been handled this time around */)
116 delayedflush <= 0;
117
118 always @(*)
119 begin
120 addr = prevaddr;
121 raddr = 32'hxxxxxxxx;
122 rd_req = 1'b0;
123 wr_req = 1'b0;
124 wr_data = 32'hxxxxxxxx;
125 busaddr = 32'hxxxxxxxx;
126 data_size = 3'bxxx;
127 outstall = 1'b0;
128 do_rd_data_latch = 0;
129 next_write_reg = write_reg;
130 next_write_num = write_num;
131 next_write_data = write_data;
132 next_outbubble = inbubble;
133 next_regs = regs;
134 cp_req = 1'b0;
135 cp_rnw = 1'bx;
136 cp_write = 32'hxxxxxxxx;
137 offset = prev_offset;
138 next_outcpsr = lsm_state == 4'b0010 ? outcpsr : cpsr;
139 next_outcpsrup = cpsrup;
140 lsrh_rddata = 32'hxxxxxxxx;
141 lsrh_rddata_s1 = 16'hxxxx;
142 lsrh_rddata_s2 = 8'hxx;
143 next_lsm_state = lsm_state;
144 next_lsr_state = lsr_state;
145 next_lsrh_state = lsrh_state;
146 next_swp_oldval = swp_oldval;
147 next_swp_state = swp_state;
148 cur_reg = prev_reg;
149
150 /* XXX shit not given about endianness */
151 casez(insn)
152 `DECODE_ALU_SWP: if(!inbubble) begin
153 outstall = rw_wait;
154 next_outbubble = rw_wait;
155 busaddr = {op0[31:2], 2'b0};
156 data_size = insn[22] ? 3'b001 : 3'b100;
157 case(swp_state)
158 2'b01: begin
159 rd_req = 1'b1;
160 outstall = 1'b1;
161 if(!rw_wait) begin
162 next_swp_state = 2'b10;
163 next_swp_oldval = rd_data;
164 end
165 $display("SWP: read stage");
166 end
167 2'b10: begin
168 wr_req = 1'b1;
169 wr_data = insn[22] ? {4{op1[7:0]}} : op1;
170 next_write_reg = 1'b1;
171 next_write_num = insn[15:12];
172 next_write_data = insn[22] ? {24'b0, swp_oldval[7:0]} : swp_oldval;
173 if(!rw_wait)
174 next_swp_state = 2'b01;
175 $display("SWP: write stage");
176 end
177 default: begin end
178 endcase
179 end
180 `DECODE_ALU_MULT: begin end
181 `DECODE_ALU_HDATA_REG,
182 `DECODE_ALU_HDATA_IMM: if(!inbubble) begin
183 next_outbubble = rw_wait;
184 outstall = rw_wait;
185 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
186 raddr = insn[24] ? op0 : addr; /* pre/post increment */
187 busaddr = raddr;
188 /* rotate to correct position */
189 case(insn[6:5])
190 2'b00: begin end /* swp */
191 2'b01: begin /* unsigned half */
192 wr_data = {2{op2[15:0]}}; /* XXX need to store halfword */
193 data_size = 3'b010;
194 lsrh_rddata = {16'b0, raddr[1] ? rd_data[31:16] : rd_data[15:0]};
195 end
196 2'b10: begin /* signed byte */
197 wr_data = {4{op2[7:0]}};
198 data_size = 3'b001;
199 lsrh_rddata_s1 = raddr[1] ? rd_data[31:16] : rd_data[15:0];
200 lsrh_rddata_s2 = raddr[0] ? lsrh_rddata_s1[15:8] : lsrh_rddata_s1[7:0];
201 lsrh_rddata = {{24{lsrh_rddata_s2[7]}}, lsrh_rddata_s2};
202 end
203 2'b11: begin /* signed half */
204 wr_data = {2{op2[15:0]}};
205 data_size = 3'b010;
206 lsrh_rddata = raddr[1] ? {{16{rd_data[31]}}, rd_data[31:16]} : {{16{rd_data[15]}}, rd_data[15:0]};
207 end
208 endcase
209
210 case(lsrh_state)
211 3'b001: begin
212 rd_req = insn[20];
213 wr_req = ~insn[20];
214 next_write_num = insn[15:12];
215 next_write_data = lsrh_rddata;
216 if(insn[20]) begin
217 next_write_reg = 1'b1;
218 end
219 if(insn[21] | !insn[24]) begin
220 outstall = 1'b1;
221 if(!rw_wait)
222 next_lsrh_state = 3'b010;
223 end
224 $display("ALU_LDRSTRH: rd_req %d, wr_req %d", rd_req, wr_req);
225 end
226 3'b010: begin
227 next_outbubble = 1'b0;
228 next_write_reg = 1'b1;
229 next_write_num = insn[19:16];
230 next_write_data = addr;
231 next_lsrh_state = 3'b100;
232 end
233 3'b100: begin
234 outstall = 0;
235 next_lsrh_state = 3'b001;
236 end
237 default: begin end
238 endcase
239
240 if ((lsrh_state == 3'b001) && flush) begin /* Reject it. */
241 outstall = 1'b0;
242 next_lsrh_state = 3'b001;
243 end
244 end
245 `DECODE_LDRSTR_UNDEFINED: begin end
246 `DECODE_LDRSTR: if(!inbubble) begin
247 next_outbubble = rw_wait;
248 outstall = rw_wait;
249 addr = insn[23] ? op0 + op1 : op0 - op1; /* up/down select */
250 raddr = insn[24] ? addr : op0; /* pre/post increment */
251 busaddr = raddr;
252 /* rotate to correct position */
253 align_s1 = raddr[1] ? {rd_data[15:0], rd_data[31:16]} : rd_data;
254 align_s2 = raddr[0] ? {align_s1[7:0], align_s1[31:8]} : align_s1;
255 /* select byte or word */
256 align_rddata = insn[22] ? {24'b0, align_s2[7:0]} : align_s2;
257 wr_data = insn[22] ? {24'h0, {op2[7:0]}} : op2;
258 data_size = insn[22] ? 3'b001 : 3'b100;
259 case(lsr_state)
260 4'b0001: begin
261 rd_req = insn[20] /* L */ || insn[22] /* B */;
262 wr_req = !insn[20] /* L */ && !insn[22]/* B */;
263 next_write_reg = insn[20] /* L */;
264 next_write_num = insn[15:12];
265 if(insn[20] /* L */) begin
266 next_write_data = insn[22] /* B */ ? {24'h0, align_rddata[7:0]} : align_rddata;
267 end
268 if (insn[22] /* B */ && !insn[20] /* L */) begin
269 do_rd_data_latch = 1;
270 outstall = 1'b1;
271 if (!rw_wait)
272 next_lsr_state = 4'b0010; /* XXX: One-hot, my ass. */
273 end else if(insn[21] /* W */ | !insn[24] /* P */) begin
274 outstall = 1'b1;
275 if(!rw_wait)
276 next_lsr_state = 4'b0100;
277 end
278 $display("LDRSTR: rd_req %d, wr_req %d, raddr %08x, wait %d", rd_req, wr_req, raddr, rw_wait);
279 end
280 4'b0010: begin
281 $display("LDRSTR: Handling STRB");
282 outstall = 1;
283 rd_req = 0;
284 wr_req = 1;
285 next_write_reg = 0;
286 case (busaddr[1:0])
287 2'b00: wr_data = {rd_data_latch[31:8], op2[7:0]};
288 2'b01: wr_data = {rd_data_latch[31:16], op2[7:0], rd_data_latch[7:0]};
289 2'b10: wr_data = {rd_data_latch[31:24], op2[7:0], rd_data_latch[15:0]};
290 2'b11: wr_data = {op2[7:0], rd_data_latch[23:0]};
291 endcase
292 if(insn[21] /* W */ | !insn[24] /* P */) begin
293 if(!rw_wait)
294 next_lsr_state = 4'b0100;
295 end else if (!rw_wait)
296 next_lsr_state = 4'b1000;
297 end
298 4'b0100: begin
299 outstall = 1;
300 rd_req = 0;
301 wr_req= 0;
302 next_outbubble = 0;
303 next_write_reg = 1'b1;
304 next_write_num = insn[19:16];
305 next_write_data = addr;
306 next_lsr_state = 4'b1000;
307 end
308 4'b1000: begin
309 rd_req = 0;
310 wr_req= 0;
311 outstall = 0;
312 next_lsr_state = 4'b0001;
313 end
314 default: begin end
315 endcase
316
317 if ((lsr_state == 4'b0001) && flush) begin /* Reject it. */
318 outstall = 1'b0;
319 next_lsr_state = 4'b0001;
320 end
321 end
322 /* XXX ldm/stm incorrect in that stupid case where one of the listed regs is the base reg */
323 `DECODE_LDMSTM: if(!inbubble) begin
324 outstall = rw_wait;
325 next_outbubble = rw_wait;
326 data_size = 3'b100;
327 case(lsm_state)
328 4'b0001: begin
329// next_regs = insn[23] ? op1[15:0] : op1[0:15];
330 /** verilator can suck my dick */
331 $display("LDMSTM: Round 1: base register: %08x, reg list %b", op0, op1[15:0]);
332 next_regs = insn[23] /* U */ ? op1[15:0] : {op1[0], op1[1], op1[2], op1[3], op1[4], op1[5], op1[6], op1[7],
333 op1[8], op1[9], op1[10], op1[11], op1[12], op1[13], op1[14], op1[15]};
334 offset = 6'b0;
335 outstall = 1'b1;
336 next_lsm_state = 4'b0010;
337 end
338 4'b0010: begin
339 rd_req = insn[20];
340 wr_req = ~insn[20];
341 casez(regs)
342 16'b???????????????1: begin
343 cur_reg = 4'h0;
344 next_regs = {regs[15:1], 1'b0};
345 end
346 16'b??????????????10: begin
347 cur_reg = 4'h1;
348 next_regs = {regs[15:2], 2'b0};
349 end
350 16'b?????????????100: begin
351 cur_reg = 4'h2;
352 next_regs = {regs[15:3], 3'b0};
353 end
354 16'b????????????1000: begin
355 cur_reg = 4'h3;
356 next_regs = {regs[15:4], 4'b0};
357 end
358 16'b???????????10000: begin
359 cur_reg = 4'h4;
360 next_regs = {regs[15:5], 5'b0};
361 end
362 16'b??????????100000: begin
363 cur_reg = 4'h5;
364 next_regs = {regs[15:6], 6'b0};
365 end
366 16'b?????????1000000: begin
367 cur_reg = 4'h6;
368 next_regs = {regs[15:7], 7'b0};
369 end
370 16'b????????10000000: begin
371 cur_reg = 4'h7;
372 next_regs = {regs[15:8], 8'b0};
373 end
374 16'b???????100000000: begin
375 cur_reg = 4'h8;
376 next_regs = {regs[15:9], 9'b0};
377 end
378 16'b??????1000000000: begin
379 cur_reg = 4'h9;
380 next_regs = {regs[15:10], 10'b0};
381 end
382 16'b?????10000000000: begin
383 cur_reg = 4'hA;
384 next_regs = {regs[15:11], 11'b0};
385 end
386 16'b????100000000000: begin
387 cur_reg = 4'hB;
388 next_regs = {regs[15:12], 12'b0};
389 end
390 16'b???1000000000000: begin
391 cur_reg = 4'hC;
392 next_regs = {regs[15:13], 13'b0};
393 end
394 16'b??10000000000000: begin
395 cur_reg = 4'hD;
396 next_regs = {regs[15:14], 14'b0};
397 end
398 16'b?100000000000000: begin
399 cur_reg = 4'hE;
400 next_regs = {regs[15], 15'b0};
401 end
402 16'b1000000000000000: begin
403 cur_reg = 4'hF;
404 next_regs = 16'b0;
405 end
406 default: begin
407 cur_reg = 4'hx;
408 next_regs = 16'b0;
409 end
410 endcase
411 cur_reg = insn[23] ? cur_reg : 4'hF - cur_reg;
412 if(cur_reg == 4'hF && insn[22]) begin
413 next_outcpsr = spsr;
414 next_outcpsrup = 1;
415 end
416
417 offset = prev_offset + 6'h4;
418 offset_sel = insn[24] ? offset : prev_offset;
419 raddr = insn[23] ? op0 + {26'b0, offset_sel} : op0 - {26'b0, offset_sel};
420 if(insn[20]) begin
421 next_write_reg = !rw_wait;
422 next_write_num = cur_reg;
423 next_write_data = rd_data;
424 end
425 if (rw_wait) begin
426 next_regs = regs;
427 cur_reg = prev_reg; /* whoops, do this one again */
428 end
429
430 st_read = cur_reg;
431 wr_data = (cur_reg == 4'hF) ? (pc + 12) : st_data;
432 busaddr = raddr;
433
434 $display("LDMSTM: Stage 2: Writing: regs %b, next_regs %b, reg %d, wr_data %08x, addr %08x", regs, next_regs, cur_reg, wr_data, busaddr);
435
436 outstall = 1'b1;
437
438 if(next_regs == 16'b0) begin
439 next_lsm_state = 4'b0100;
440 end
441 end
442 4'b0100: begin
443 outstall = 1;
444 next_outbubble = 0;
445 next_write_reg = insn[21] /* writeback */;
446 next_write_num = insn[19:16];
447 next_write_data = insn[23] ? op0 + {26'b0, prev_offset} : op0 - {26'b0, prev_offset};
448 next_lsm_state = 4'b1000;
449 $display("LDMSTM: Stage 3: Writing back");
450 end
451 4'b1000: begin
452 outstall = 0;
453 next_lsm_state = 4'b0001;
454 end
455 default: $stop;
456 endcase
457 if ((lsm_state == 4'b0001) && flush) begin /* Reject it. */
458 outstall = 1'b0;
459 next_lsm_state = 4'b0001;
460 end
461 $display("LDMSTM: Decoded, bubble %d, insn %08x, lsm state %b -> %b, stall %d", inbubble, insn, lsm_state, next_lsm_state, outstall);
462 end
463 `DECODE_LDCSTC: if(!inbubble) begin
464 $display("WARNING: Unimplemented LDCSTC");
465 end
466 `DECODE_CDP: if(!inbubble) begin
467 cp_req = 1;
468 if (cp_busy) begin
469 outstall = 1;
470 next_outbubble = 1;
471 end
472 if (!cp_ack) begin
473 /* XXX undefined instruction trap */
474 $display("WARNING: Possible CDP undefined instruction");
475 end
476 end
477 `DECODE_MRCMCR: if(!inbubble) begin
478 cp_req = 1;
479 cp_rnw = insn[20] /* L */;
480 if (insn[20] == 0 /* store to coprocessor */)
481 cp_write = op0;
482 else begin
483 if (insn[15:12] != 4'hF /* Fuck you ARM */) begin
484 next_write_reg = 1'b1;
485 next_write_num = insn[15:12];
486 next_write_data = cp_read;
487 end else begin
488 next_outcpsr = {cp_read[31:28], cpsr[27:0]};
489 next_outcpsrup = 1;
490 end
491 end
492 if (cp_busy) begin
493 outstall = 1;
494 next_outbubble = 1;
495 end
496 if (!cp_ack) begin
497 $display("WARNING: Possible MRCMCR undefined instruction: cp_ack %d, cp_busy %d",cp_ack, cp_busy);
498 end
499 $display("MRCMCR: ack %d, busy %d", cp_ack, cp_busy);
500 end
501 default: begin end
502 endcase
503
504 if ((flush || delayedflush) && !outstall)
505 next_outbubble = 1'b1;
506 end
507endmodule
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