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Add a .gitattributes file to force hex files to be binary-like.
-rw-r--r-- 24 .gitattributes blob | blame | history | raw
-rw-r--r-- 3290 ARM_Constants.v blob | blame | history | raw
-rw-r--r-- 1029 BlockRAM.v blob | blame | history | raw
-rw-r--r-- 463 BusArbiter.v blob | blame | history | raw
-rw-r--r-- 2712 DCache.v blob | blame | history | raw
-rw-r--r-- 8941 Decode.v blob | blame | history | raw
-rw-r--r-- 8980 Execute.v blob | blame | history | raw
-rw-r--r-- 1093 Fetch.v blob | blame | history | raw
-rw-r--r-- 2434 ICache.v blob | blame | history | raw
-rw-r--r-- 9182 Issue.v blob | blame | history | raw
-rw-r--r-- 13874 Memory.v blob | blame | history | raw
-rw-r--r-- 1472 RegFile.v blob | blame | history | raw
-rw-r--r-- 1119 Terminal.v blob | blame | history | raw
-rw-r--r-- 1146 Writeback.v blob | blame | history | raw
-rw-r--r-- 1427 ram.comments.hex blob | blame | history | raw
lrwxrwxrwx 13 ram.hex -> tests/ram.hex blob | blame | history | raw
-rw-r--r-- 9624 system.v blob | blame | history | raw
-rw-r--r-- 1278 testbench.cpp blob | blame | history | raw
drwxr-xr-x - tests tree | history
FireARM pipelined ARM-like CPU implementation in Verilog
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